[NRF5340] How does the ADC gain block work and what does the EG1/6 to EG1 7.29.12.1 SAADC Electrical Specification mean

[SyedSajid]

How does the ADC gain block work.

• Suppose using Vdd=3.3V as ADC reference, analog signal input from 0 to 3V and gain 1/4 
  1. What will be the ADC core voltage for single ended ADC measurement
     is it 0 to VDD/4 ( 0 to 0.825V) or double 0 to Vdd/2 ( 0 to 1.65V)
  2. WIll the input signal to the ADC will be scaled down by 1/4 internally ?

What does the EG1/6 to EG1 in 7.29.12.1 SAADC Electrical Specification mean?
Does it mean ADC gain error ? or is the scaling error ?

[haakonsh]

1. The input range is 0-VDD with a reference at VDD/4. This means that you will need to set the appropriate gain, f.ex. 1/4, in order to scale the input voltage range to the reference voltage range. 
   
   
2. See (1).
   
   
3. The error in the gain stage has not yet been characterized on the nRF5340, but I would be surprised if it was not very similar to the nRF52's SAADC electrical specification.
   It is error/noise introduced in the gain stage, without any input offset.  

[SyedSajid]

Thanks Haakonsh, on your point 3 the error specification mentioned  is it before performing any calibration on the gain/offset or after 

[haakonsh]

The gain error is independent of any offset calibration. Gain calibration is done during manufacturing, so the error from the gain stage is characterized after gain calibration.