Schematic Review for VDD_GPIO

[austinaoe]

Hi there!

I have a host microcontroller connected to the nrf91.  The host microcontroller will enabling the nrf9160 through the enable line.  From the documentation, VDD_GPIO should be floating when the enable line is low.  I'm wondering if I'm implemented the circuit correctly...please let me know your thoughts! 

[Kaja]

Hi, 

this seems to be correct.

Some other notes:
1. C60 should be placed closes to the VDD_GPIO pin.
2. Change the placement of C62 and C55, C62 closes to the VDD pin.
3. Change the placement of C61 and C54, C61 closes to the VDD pin.


For a full review, please upload the hole schetmatic.

Best regards,
Kaja

[austinaoe]

https://www.dropbox.com/t/EVDFzQEvq7PQMYHS

Thank you!  Here is my schematic

[Kaja]

Could you upload the file, directly to devzone using --> instert --> image/video/file 

If you want the file to be confidential make the case private.

Best regards,
Kaja

[austinaoe]

Model_A_Board.pdf

[Kaja]

The rest look okay. 

Bet regards,
Kaja

[austinaoe]

Is it correct to have the enable line of the nrf9160 connected to the ldo of VDD_GPIO?  What is the typical/recommended way to achieve this?

[Kaja]

In our reference we control it via the VDD power, but this depends on the specific design's recruitments. 

Best regards,
Kaja