This post is older than 2 years and might not be relevant anymore
More Info: Consider searching for newer posts

timers in nrf5340

Hello,

1) In nrf5340 app CPU,  there are only 3 timer I can use, timer0, timer1 and time2, is it right?

2) I want to use four timers in my project, to control two SPI. now I only have 3 timers, what can I do to get the fourth timer? Do I need to use one timer in Net CPU? if yes, how?

Thanks a lot.

Carl

Parents Reply
  • Carl Sun said:
    Can I use the Zephyr kernel timer with DPPI? 

     No, I don't think that is possible.

    want to use four timers in my project, to control two SPI
    Carl Sun said:
    I need a timer which minimum duration is 20 μs

    So you are generating an event every 20 µs using the TIMER, in order to control the SPI? Could you explain this some more? I don't understand why this is needed.

Children
  • Every 20 µs I need to send a command through two SPI to DAC, so I need four timers which duration are 20µs(each SPI need two timers), it works with the three times and DPPI. Can the duration of the timer from Zephyr kernel be 20 µs? If not, can I get the fourth timer with the 20 µs duration?

    Thanks.

    Carl 

  • Yes, I want to generate an event every 20 µs using the TIMER, in order to control the SPI. We need the frequency to be extremely fast. It works with the three TIMERs(together with DPPI)

    Can the timer from Zephyr be 20 µs?

    Thanks.

  • Hi Carl,

    Carl Sun said:

    Can the timer from Zephyr be 20 µs?

     No, the Zephyr kernel timer uses the RTC peripheral(32.768 kHz clock), so you get ~30 us resolution, and it's not possible to use (D)PPI with it. So TIMER seems to fit your use-case better.

    Note that with the TIMER, you have 6 capture compare channels, so you might not need to use all TIMERS instances. e.g. use TIMER1 CC[0] for one SPI, and TIMER1 CC[1] for the other SPI. But if that is not possible for your use-case, and you need an additional TIMER, then yes, it looks to be possible to get the network core TIMER to generate events to the application core, by using the interprocessor communication (IPC) peripheral. See figure 3 at this link.

Related