nRF5340 LFXO Internal Load Cap Setting

[Akash Patel]

Hello,

I am looking at the schematic for the nRF5340 DK and see that there are no external load capacitors for the 32 kHz crystal which has C_L = 9 pF. Therefore, we are relying on the nRF5340 internal load capacitor feature through firmware. Looking here, I see that it is set to 6 pF by default. Looking here in the PS, I see that C_pin is either 6, 7, or 9 pF if you have the internal capacitors enabled and given that we are setting it to 6 pF, I assume this means that C_pin = 6 pF. Now assuming that C_pcb = 1 pF and C1 = C2 = 0 (because there are no external capacitors), using the formula here, I find that C1' = C2' = 7 pF and C_L is therefore 3.5 pF which does not equal the C_L of the crystal (9 pF). Even if I set the internal load capacitor register to the maximum of 9 pF, I only get C_L = 5 pF. How should this register be set properly to prevent the need for external load capacitors? Seems I am missing something in the calculation.

Regards,

Akash Patel

[JONATHAN LL]

Hi Akash,

I believe you are correct but have forwarded the question to the designer so will update you when we have a proper answer. 

Regards,
Jonathan

[JONATHAN LL]

When the 9pF is selected internally then that is actually a 18pF capacitors for each pin, so C1 = 18pF and C2 = 18pF, that makes the value of CL = 9pF. So if the device spec says crystal needs CL to be 9pF then you can select internal 9pF. 

There will be some updates to the docs to help clarify. 
Regards,
Jonathan

[Akash Patel]

Hi Jonathan,

If that is indeed the case, the firmware by default is selecting 6pF here and I don't think that is being changed with any of the overlays or files while the crystal is specifying a C_L of 9pF causing a discrepancy. Can you look into this?

Regards,

Akash

[JONATHAN LL]

New update with some corrections here.

There will be a update in the PS that hopefully addresses this issue in a proper way as it is inconsistent at best right now. 

The 6pF is correct, but a bitt difficult to understand from the docs. The real value is closer to 9pF due to stray capacitance in the XL1 and XL2 pins.

So the the internal load capacitance (I_CL) for the LF on the nrf53 has the options 6pF, 7pF and 9pF, these values will result in a load capacitances (C_L) equal to the I_CL plus the stray capacitance from the PCB (pad and routing capacitance), it is approximately 3pF.

So that gives us  C_L =   I_CL + 3pF,  and in the case of the nrf53 DK that has a crystal that wants a max C_L of 9pF we sett the I_CL to 6pF and add the 3pF form stray PCB capacitance and we get the 9pF we want. 

So the previous answer was not that great.

Regards,
Jonathan

[Akash Patel]

Hi Jonathan,

I marked the answer as verified but then later came back to this and realized the math still isn't working out for me. So if we set I_CL = 6pF (through the register) and there is 3pF capacitance from the pad, we get a total of 9pF for both C1' and C2'. But then using the formula for C_L (figure 24 in the PS), we only get 4.5 pF. I think there is still something wrong.

Regards,

Akash