How does the interrupt latency compare between COMP/LPCOMP and GPIOTE? Are tLPCANADET and tPROPDLY the correct field to be looking at in the specification? The electrical specification for GPIOTE on nRF52833 is missing on the infocenter.
How does the interrupt latency compare between COMP/LPCOMP and GPIOTE? Are tLPCANADET and tPROPDLY the correct field to be looking at in the specification? The electrical specification for GPIOTE on nRF52833 is missing on the infocenter.
Hi,
here is a link to GPIO Electrical Specification, in the info center.
Best regards,
Kaja
It doesn't say much about the latency of a GPIO interrupt though. Basically I'm just wanting to know how long I can expect between a change on the input and some code being run, and how that compares between LPCOMP, COMP and GPIOTE.
Unfortunately we don't have detailed numbers that you may compare here. I guess you would need to measure them yourself if they are critical, e.g. from toggling the input until the interrupt handler is toggling an output.
You can find some values here also that may be relevant, since the CPU will may need to startup if the chip is in idle or sleep:
https://infocenter.nordicsemi.com/topic/ps_nrf52833/power.html#unique_1449636937
It looks like it's mostly in the lower ~us range, so I would not expect a big difference.
Kenneth