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No LF CLK started event after start LF clock

We encounter 52810 freezing problem.
It occurses in low probability less than 1 out of 1000.

Power-on reset is no use for this problem.
The freezed 52810 chip restored when we erase and reprogram it with the same soft.

We also trace the problem in the freezed 52810 chip by J-Link Debugger.
And find it stoppes in LF Clock init at user application.

The freezed part of source is below

static nrf_drv_clock_handler_item_t m_clock_handler_item = {
    .p_next = NULL,
    .event_handler = clock_event_handler,
};

static void clock_event_handler(nrf_drv_clock_evt_type_t event)
{
    if (event == NRF_DRV_CLOCK_EVT_LFCLK_STARTED) {
        lfclk_started = 1;
    }
}

void clock_lfclk_start(void)
{
    lfclk_started = 0;
    nrf_drv_clock_lfclk_request(&m_clock_handler_item);
    while (lfclk_started == 0) {  }
}

The while loop in clock_lfclk_start function will be breaked when the callback routine executed by LF CLK STARTED irq.
But it seems there is no LF CLK STARTED irq assert in problem 52810 chip.

There is only 32M HF crystal outside 52810 in our board, and NRFX_CLOCK_CONFIG_LF_SRC is 2(SYNTH).
We are using SDK v15.0.0

Do you have any idea about this issue?

  • Hello,

    There is only 32M HF crystal outside 52810 in our board, and NRFX_CLOCK_CONFIG_LF_SRC is 2(SYNTH).
    We are using SDK v15.0.0

    Thank you for clarifying this. Synthesizing the LFCLK from the HFCLK will require the HFCLK to always be active - this will increase power consumption by quite a lot, compared to having a dedicated LF source.
    I am sure you already know this, but I thought I should mention it in any case.

    The while loop in clock_lfclk_start function will be breaked when the callback routine executed by LF CLK STARTED irq.
    But it seems there is no LF CLK STARTED irq assert in problem 52810 chip.
    Do you have any idea about this issue?

    The fact that you are seeing this in 'less than 1 out of 1000', I am thinking we need to look closer at the HFCLK source.
    Do you have access to equipment to measure the 32 MHz crystal, to see if it performs as expected? Or, do you receive the HFCLK started event prior to waiting for the LFCLK event?
    Could you try to change your LFCLK source and configuration to the following, and see if the issue persists in the problem device?

    // <o> NRF_SDH_CLOCK_LF_SRC  - SoftDevice clock source.
     
    // <0=> NRF_CLOCK_LF_SRC_RC 
    // <1=> NRF_CLOCK_LF_SRC_XTAL 
    // <2=> NRF_CLOCK_LF_SRC_SYNTH 
    
    #ifndef NRF_SDH_CLOCK_LF_SRC
    #define NRF_SDH_CLOCK_LF_SRC 0
    #endif
    
    // <o> NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. 
    #ifndef NRF_SDH_CLOCK_LF_RC_CTIV
    #define NRF_SDH_CLOCK_LF_RC_CTIV 16
    #endif
    
    // <o> NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. 
    // <i> How often (in number of calibration intervals) the RC oscillator shall be calibrated
    // <i>  if the temperature has not changed.
    
    #ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV
    #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 2
    #endif
    
    // <o> NRF_SDH_CLOCK_LF_ACCURACY  - External clock accuracy used in the LL to compute timing.
     
    // <0=> NRF_CLOCK_LF_ACCURACY_250_PPM 
    // <1=> NRF_CLOCK_LF_ACCURACY_500_PPM 
    // <2=> NRF_CLOCK_LF_ACCURACY_150_PPM 
    // <3=> NRF_CLOCK_LF_ACCURACY_100_PPM 
    // <4=> NRF_CLOCK_LF_ACCURACY_75_PPM 
    // <5=> NRF_CLOCK_LF_ACCURACY_50_PPM 
    // <6=> NRF_CLOCK_LF_ACCURACY_30_PPM 
    // <7=> NRF_CLOCK_LF_ACCURACY_20_PPM 
    // <8=> NRF_CLOCK_LF_ACCURACY_10_PPM 
    // <9=> NRF_CLOCK_LF_ACCURACY_5_PPM 
    // <10=> NRF_CLOCK_LF_ACCURACY_2_PPM 
    // <11=> NRF_CLOCK_LF_ACCURACY_1_PPM 
    
    #ifndef NRF_SDH_CLOCK_LF_ACCURACY
    #define NRF_SDH_CLOCK_LF_ACCURACY 1
    #endif



    Best regards,
    Karl

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