NRF52840 SAADC dma data order change after debug-break

[Alex_T]

Hi,

I am using SAADC with multiple channels in my application and I discovered data order does change after a debug-break.

To reproduce I used the saadc example from the library "saadc_pca10056" (nRF5_SDK_for_Thread_and_Zigbee_v4.1.0) and simply added a second channel. I connected P0.02 to VCC and P0.03 to GND.

void saadc_init(void)
{
    ret_code_t err_code;
    nrf_saadc_channel_config_t channel_config =
        NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(NRF_SAADC_INPUT_AIN0);

    nrf_saadc_channel_config_t channel_config2 =
        NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(NRF_SAADC_INPUT_AIN1);

    err_code = nrf_drv_saadc_init(NULL, saadc_callback);
    APP_ERROR_CHECK(err_code);

    err_code = nrf_drv_saadc_channel_init(0, &channel_config);
    APP_ERROR_CHECK(err_code);

    err_code = nrf_drv_saadc_channel_init(1, &channel_config2);
    APP_ERROR_CHECK(err_code);

    err_code = nrf_drv_saadc_buffer_convert(m_buffer_pool[0], SAMPLES_IN_BUFFER);
    APP_ERROR_CHECK(err_code);

    err_code = nrf_drv_saadc_buffer_convert(m_buffer_pool[1], SAMPLES_IN_BUFFER);
    APP_ERROR_CHECK(err_code);

}

And changed the buffer size to an even number:

#define SAMPLES_IN_BUFFER 6

Then after running the application a few seconds I pause in the debugger and watch "m_buffer_pool". First item is ~840cnts (VCC) and second ~0cnts (GND). This is as expected as AN0 (VCC) is measured in channel0 and AN1 (GND) is measured in channel1.

Now pressing continue in the debugger, wait for a few seconds and pause again. Now items are swapped - first item is ~0cnts (GND) and second item ~840cnts (VCC). Now continue and pause does not change the order back.

Why is the data order swapped after a debug break?!

I have seen the same behavour on NRF52833 as on NRF52840.

Thanks in advance,

Alex

[Jared]

Hi,

To reproduce I used the saadc example from the library "saadc_pca10056" (nRF5_SDK_for_Thread_and_Zigbee_v4.1.0) and simply added a second channel. I connected P0.02 to VCC and P0.03 to GND.

 The example uses PPI which means that data is retrieved without going through the CPU. Pausing the CPU with the debugger will therefore not pause the PPI which will make the sampling unsynchronized. This is as expected. 

regards

Jared 

[Alex_T]

Hi,

Thank you for the quick reply.

Yes, PPI and DMA make receiving possible without depending on CPU. DMA is responsible for reading ADC data and writing it to RAM.

So from my understanding there should be no change in the data order when the CPU is stopped as the CPU is not involved in this process anyways. Data stream might stop because CPU is not updating buffers but I don't get yet why the order in my buffer is changed and how to prevent it.

How can I debug/break & continue my application without facing this problem?

Thanks,

Alex

[Jared]

Hi,

The issue is a variant of the buffer swap issue described here. Basically, the CPU is prevented from triggering the START task before the next SAMPLE task because it's halted by the debugger. PPI however will trigger the SAMPLE task since it runs outside of the CPU. 

All of this is as expected. The thread I linked has some suggestions for workarounds.

best regards

Jared