Strange I2C/TWI Pullup Behaviour NRF53

[bsams]

We're developing on a custom NRF53 board. With the I2C bus disconnected from all peripherals, but with external 10k pullups connected, we get the following waveform when attempring a transaction at 400kHz (yellow SCL, blue SDA):

It shows the device attempting to communicate (with its system voltage at 3.3V) and seems normal. If we remove the external pullups, however, then we get this:

As far as we can tell on the software side, the internal pullups are enabled, so its not clear why the waveform would be significantly different (and have strange timing)

[Jørgen Holmefjord]

Hi,

Can you read the GPIO register configuration for the pins used with TWI peripheral from the debugger, to make sure that the pull resistors are actually enabled?

If you are using our drivers, this should be enabled by default, but it would be good to rule out this as the source of the issues.

Best regards,
Jørgen

[Jørgen Holmefjord]

Thanks, yes it looks to be enabled.

Have you tried running the same firmware on a nRF5340 DK, to see if the signals look the same there? 

You can also try to configure the GPIOs in High Drive (or even Extra high drive for P1.02/P1.03 pins), to see if that resolves the issue. You can use gpio_pin_configure() and the GPIO drive strength flags to configure drive strength of the GPIOs in NCS.

[bsams]

Hey Jorgen,

Our FW and HW is custom, so it is difficult to port it to the DK. My understanding of the drive strength is that it would affect the fall time, not the rise time?

Thanks,

Ben

[Jørgen Holmefjord]

bsams said:

Our FW and HW is custom, so it is difficult to port it to the DK.

Ok, I still think it would be good to rule out board issues. Do you see the same behavior with I2C/TWI slave(s) connected to the bus? 

bsams said:

My understanding of the drive strength is that it would affect the fall time, not the rise time?

Yes, since it is configured with S0D1 by default (Standard '0'. disconnect '1'), I believe you are correct that it should not affect rise time.

[bsams]

Hey Jorgen,

I think we've found the reason for the strange voltage, it looks like in some modes the SCL/SDA lines are ties together with 20k, so the internal pullups are active but the SCL is being pulled down by the SDA. It doesn't quite explain the timing change though, can I check if its because the peripheral is waiting for the line to go high again because it thinks the clock is being stretched, and then timing out because its limiting the amount of clock stretching allowed?

Thanks,

Ben

[Jørgen Holmefjord]

Hi,

bsams said:

in some modes the SCL/SDA lines are ties together with 20k

Is this a mode on your board, or do you see the nRF5340 tie these lines together?

bsams said:

can I check if its because the peripheral is waiting for the line to go high again because it thinks the clock is being stretched

Unfortunately, there is no events indicating that a clock stretch is ongoing, and there is also no status-register in the TWIM peripheral that will indicate this. I' not sure how else this could be checked.

bsams said:

and then timing out because its limiting the amount of clock stretching allowed

As far as I know, there is no timeout/maximum allowed time for clock stretching.

Best regards,
Jørgen