SES no long knows the $(Target), the simulator or the device register maps.

[Jordan Archer]

I recently moved my custom board definition from the zephyr board dir to the nrf board dir, to unify my changes into on git repo for internal use.  I think that's when the Segger Embedded Studio stopped knowing the $Target and the JLINK debug interface.  Along with the nrf53 device register groups.  

If I manually set the target and the debugger to jlink, it can debug find, but it loses this when I exec SES.  It also does not know about other register groups such as GPIOTE and all others.

Is there a fix for this?  Where does SES store that infomation?

[Jordan Archer]

I've uploaded the two sub-dirs that go under the v1.6.0\nrf directory, that is a test project that shows the same issue.

https://drive.google.com/file/d/1KBU998V3ivDfhtBd0iV1CmIz0i9tRU78/view?usp=sharing

[Jordan Archer]

And manually loading the location of the svd file did not work either. 

[Jordan Archer]

Here is the full tree.

https://drive.google.com/file/d/12iZSfdKLBS_787szd4N28Y2eik4bbrcw/view?usp=sharing

The project dir is under v1.6.0\nrf\projects\onedrop_pod.

[run_ar]

Hi Jordan,

I've tried to open your project a few times now, unfortunately I have not been able to do so. Are you using the toolchain manager? or some different installation?

[Jordan Archer]

Toolchain manager.

[Vidar Berg]

This thread may be relevant: https://devzone.nordicsemi.com/f/nordic-q-a/80029/failed-to-write-memory-when-using-segger-embedded-studio-and-nrf-connect-sdk/331863. You may want to check if the chip variant in your board file matches the one used in the python script I refered to.

[Jordan Archer]

Can you open the project under?  And it appears that if you run cmake, SES loses all of the device and jlink info.  

nrf\projects\onedrop_pod\build_onedrop_cpuapp_pod1

The files:

CMakeCache.txt Output build.ninja mcuboot onedrop_pod.emSession regions.yml zephyr_modules.txt
CMakeFiles app cmake_install.cmake modules partitions.yml rules.ninja zephyr_settings.txt
Kconfig build.emProject hci_rpmsg onedrop_pod.emProject pm.config zephyr

[Vidar Berg]

I was able to build 'build_onedrop_cpuapp_pod1' after I ran a 'west update'. It appeared to be an issue with the Zephyr repo.

Anyway. I think I found the issue now: the python script responsible for generating the Segger project assumes the board file will include the SoC devicetree file at the top of the file, but your onedrop_cpuapp_pod1.dts file does not do that. Instead it includes it via your onedrop_cpuapp_base.dts file.

Here is the part from the script that attempts to parse the include string from the board file:

    file = open(boardDir + "/" + boardName + ".dts", "r")
    dtsfile = file.read()
    file.close()

    deviceName = ""
    segments = ""
    svdFile = ""
    n = dtsfile.find("#include <nordic/")
    if n != -1:
        m = dtsfile.find(".dtsi>")
        if m != -1:
            device = dtsfile[n + 17:m]
            if device == "nrf51822_qfaa":
                deviceName = "nRF51822_xxAA"
                segments = ("FLASH RX 0x00000000 0x00040000;"
                            "RAM RWX 0x20000000 0x00004000")
                svdFile = "nrf51.svd"

To fix this, please use the following includes in onedrop_cpuapp_pod1.dts:

/dts-v1/;

#include <nordic/nrf5340_cpuapp_qkaa.dtsi>

#include "onedrop_cpuapp_base.dts"

Then remove the SoC include from onedrop_cpuapp_base.dts:

/*

 * Copyright (c) 2020 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: Apache-2.0

 */

#include "nrf5340_cpuapp_common.dts"

/ {

    compatible = "OneDrop";

[Jordan Archer]

So that appears to help.  Thanks. 

And it may be my own lack of knowledge, but I have three boards that I'm developing for.  Their basic features are the same, but some pins shuffle.  Am I taking the right approach of having a dts for each board, but including the base design dts?

[Vidar Berg]

Thanks for confirming that it worked.

It sounds like a reasonable approach to me. I think the only other option would have been to have a board file for your base design, then used board overlays in the project directory to override the default pinout.