Question on QSPI registers CINSTRCONF and CINSTRDAT0

[sshenoy105]

Hello,

nrf5340 datasheet -> nRF5340_OPS_v0.5

section: 7.1.26.7 Sending custom instructions (Page: 383)

1. we can send an instruction consisting of a one-byte opcode and up to 8 bytes of additional data and to read its response.
2. After a custom instruction has been sent, the CINSTRDAT0 and CINSTRDAT1 will contain the response bytes from the custom instruction.

Question is if the data in CINSTRDAT0 and CINSTRDAT1  contain ONLY bits that come in via SIO1  as shown in Figure 116 in the very next page ? The figure seems to indicate that no data is expected (or is ignored)  unless it's coming in via SIO1. and this is not really clear from in the text  in 7.1.26.7  section.  Can you clarify ?

what if a slave device sends data back on SIO0 (there are a few display controllers that do that).. is there anything we can do to access data that is coming via SIO0 ?

[Simonr]

Hi

First off, is there a reason you're using the nRF5340 OPS (v0.5) instead of the official product specification? The OPS was intended for the engineering ICs, and can not be counted as complete.

I assume this is the figure you're referring to (it's no longer Figure 116 in the latest PS revision).

Are you expecting the custom instruction to be written over all 4 IOs? As stated in section 7.25.7 Sending custom instructions: "The custom instruction is sent when the CINSTRCONF register is written and it is always sent on a single data line SPI interface." Which is why all custom instruction data goes over IO0 and IO1.

Best regards,

Simon

[sshenoy105]

ok.. I looked at the latest datasheet and it is not much different as far as the context is concerned (please correct me if i missed anything there).. the question remains though since you did not answer what I had highlighted..

Are you expecting the custom instruction to be written over all 4 IOs?
No.. It is clear to me how custom instruction works from POV of sending it from MCU 

what I want to know is  if the response data )from QSPI slave)  in CINSTRDAT0 and CINSTRDAT1  contain ONLY bits that come in via SIO1  as shown in Figure 4 .  As in MCU sends command/data in SIO0 and does MCU expect the response from QSPI slave ONLY in SIO1 ? The reason I ask is many display controllers, sense what's coming in via SIO0 and send response on the same SIO0 line.. can you please confirm ?