nRF52810 pin hardware architecture

[gschelotto]

Hi,

I'd need some information I'm not able to find in product specification v1.3:

• What is the architecture of the GPIO / AN pins of this device? Input protection diodes, pull-up/down, output open drain, push-pull, etc
• What is the state of the all pins during the power-up? For example pin4 of QFN48 package is a digital or an analog input?
  
• Can I configure any digital pin as MISO, MOSI, SCLK or CS?

thanks in advance,
gaston

[ketiljo]

What is the architecture of the GPIO / AN pins of this device? Input protection diodes, pull-up/down, output open drain, push-pull, etc

All pins have ESD protection diodes. All pins can have pull-up/down. Output is push-pull only

What is the state of the all pins during the power-up? For example pin4 of QFN48 package is a digital or an analog input?

During power up, all pins are disconnected, i.e. high Z.

Can I configure any digital pin as MISO, MOSI, SCLK or CS?

You can configure the digital interfaces to any pin. Only the analog inputs are fixed.

 

 

[gschelotto]

ketiljo said:

All pins have ESD protection diodes.

ketiljo said:

During power up, all pins are disconnected, i.e. high Z.

These are the points I'd need to clarify. ESD diodes are before or after the disconnected input?

My main concern is that in my application I have some uC pins tied to 4.5V (not the uC main 3V3 power supply ) and when the uC is OFF I need to avoid this picture:

Could you confirm this?

gaston

[Dmitry]

ESD diodes are placed at pin entry - they protect a circuit regardless of its state.

In your case, you will have voltage above VDD+0.3 at your pin that may cause damage of uC. Is there any specific reason to tie 470k to 4.5V, not Vcc?

[ketiljo]

The ESD diodes are always present. Max voltage on any GPIO pin is VDD+0.3 V. So in the case when VDD = 0 V, max voltage o the pin is 0.3 V. Else you will back power the device via the GPIO and the ESD diode. 

But given that you have a 470 kohm pullup resistor, this will limit the current to (4.5 - 0.3) / 470k = 9 µA. 

This is safe so you're ok here. 

[gschelotto]

Not 4.5V but 4.2V instead. This is the max. LiPo Battery that I use to implement an ON/OFF system control. I do not know how to do without this. 

gaston

[gschelotto]

Yes it is safe. However I've have experienced strange behaviors in similar designs with generated voltages around 2-2.5V on VDD due to undesired input currents when VDD is OFF. Sometimes this is enough to power up the uC with without powering VDD from LDO or DDC/DC.

gaston

[Dmitry]

Yes, with low-power MCU it's a common issue - if some pin is externally powered even through high resistance, it will feed and accumulate charge on VDD until it reaches a startup threshold, then MCU will try to start, quickly discharging capacitors - and so on.

I would not even say that this design is safe - when MCU is sleeping, its power consumption can be lower than 1uA, and 9uA passing through the pin can raise the voltage on VDD up to ~4V if there are no limiting components.

[gschelotto]

Okay, everything that occurs to me is to do an experimental test.

I just made a check connecting the pin P0.07 of an NRF51822 to 3V (assuming it has the same pinmux architecture as the NRF52810) and unpowering the rest of the system. The result is that a voltage of 2.38V appears on VDD that finally powering the uC.

If I power the P0.07 through a 470k pull-up resistance the generated voltage falls to 500mV. This is not enough to start the uC but it is still undesirable.

Even though the uC pins are disconnected during the power-Up, I don't feel confident about the hardware configuration that I had suggested. I will have to think about a safer alternative.

For me we can close this case. Thank you Ketiljo and Dmitry for your help!

regards,
gaston