nRESET/DIO pin specifications? recommended filtering, inconsistent state between resets.

[Robin]

As noted in recent past cases, we have an issue with the state of the nRESET pin that is causing unwanted resets when connected/disconnected from external hardware (programmer, battery charger.

In testing for state of the pin between resets (forced and unwanted), it is found to randomly come up either internally pulled up, or floating, and either immune to resets, or not. Adding an external 1K pullup has appeared helped to some marginal degree, but is not fully reliable. We have scoped the pint and there is invariably a significant glitch on the pin the characteristics of which seem to change based on, presumably, internal termination and/or other reset parameters.  There appears to be 3 fundamental conditions that the pin comes up in:

     1.)  Floating, in which case, any attempted connect or disconnect causes the chip to reset (most prevalent)

     2.)  Internally pulled up, in which case, connect may or may not cause a reset, and

     3.) Unknown pullup, but never resets when connected/disconnected (presumably somehow placed in debug mode?)

At any rate, we need to design some level of filtration ahead of this pin (and perhaps the SWCLK pin) to eliminate these unwanted resets, without affecting programmability. 

However, There appears to be no specifications in the documents for these pins that describe threshold levels and timing requirements for the reset and programming interfaces.

Can someone please help with this by either providing a "know to work"  pin cushioning circuit, or the specification for these pins to start a filter design?

Thank you all kindly,

Robin @ TL 

[Kenneth]

Hi,

There is an internal 47kohm pull-up on nRESET/SWDIO pin. The chip will be kept in reset state until the input level reach logic high (>0.7 * VDD). The time this will take depend on external circuity, for instance additional external pull-up resistors and possible capacitance from pads, traces and additional external capacitors placed on the nRESET/SWDIO pin.

You are free to add any additional circuitry you see fit, e.g. a capacitor or small resistor, the impact will be the time the chip is kept in reset state before logic high is reached. It may also impact max clock frequency during programming.

Best regards,
Kenneth 

3.) Unknown pullup, but never resets when connected/disconnected (presumably somehow placed in debug mode?)

Correct. 

[Robin]

Hello Kenneth,

Good to chat with you again. .

One of the points you haven't addressed is why the pin itself would boot up to different termination states, and, by the way sometimes ends up in a state that the programmer cant find the chip, even though our code appears to be running (a condition I failed to mention before, sorry) 

Also, I have found no ref docs that suggest or imply that any external additional circuitry for "proper" function.

W/R/T specifications:

1.) Are there any rise/fall/hold times that need to be met for programming and/or reset function?

2.) Where is the 47K pull up documented?  Is it supposed to always be there?  My testing indicates it inconsistent and when there more like 10 - 20K when there and >100k after some resets..  

3.) What is the input voltage required for a logic low.  If as a GPIO, the spec is strangely written.  It appears that it could need to be pulled all the way to 0.00 volts before it will change. Can you clarify this spec please?

Finally, do you have any ideas why the chip wouldn't be recognized by the programmer?  The only way I can recover is to hold power low on the board until just after the program command is initiated.  Sometimes ot takes several attempts before successful programming occurs.

Thanks again,

Robin @ TL