As noted in recent past cases, we have an issue with the state of the nRESET pin that is causing unwanted resets when connected/disconnected from external hardware (programmer, battery charger.
In testing for state of the pin between resets (forced and unwanted), it is found to randomly come up either internally pulled up, or floating, and either immune to resets, or not. Adding an external 1K pullup has appeared helped to some marginal degree, but is not fully reliable. We have scoped the pint and there is invariably a significant glitch on the pin the characteristics of which seem to change based on, presumably, internal termination and/or other reset parameters. There appears to be 3 fundamental conditions that the pin comes up in:
1.) Floating, in which case, any attempted connect or disconnect causes the chip to reset (most prevalent)
2.) Internally pulled up, in which case, connect may or may not cause a reset, and
3.) Unknown pullup, but never resets when connected/disconnected (presumably somehow placed in debug mode?)
At any rate, we need to design some level of filtration ahead of this pin (and perhaps the SWCLK pin) to eliminate these unwanted resets, without affecting programmability.
However, There appears to be no specifications in the documents for these pins that describe threshold levels and timing requirements for the reset and programming interfaces.
Can someone please help with this by either providing a "know to work" pin cushioning circuit, or the specification for these pins to start a filter design?
Thank you all kindly,
Robin @ TL
