Spike in MISO line at end SPI transmission

[mgh]

We have an nRF52840 connected to a SAM4e over SPI. The nRF52840 is the slave and the SAM4e is the master. The 52840 uses a SPI slave routine based on the SDK17 SPIS example code. The SPI 52840 initialization is:

   spis_config.csn_pin  = SELECT_PIN;
    spis_config.miso_pin = MISO_PIN;
    spis_config.mosi_pin = MOSI_PIN;
    spis_config.sck_pin  = SCK_PIN;

    spis_txLlength = 0;
    spis_rxLlength = MAX_SPIS_RX_BUFFER_SIZE;

    memset(spis_rxBuf, 0, MAX_SPIS_RX_BUFFER_SIZE);
    memset(spis_txBuf, 0, MAX_SPIS_TX_BUFFER_SIZE);

    APP_ERROR_CHECK( nrf_drv_spis_init( &spis, &spis_config, spis_eventHandler ) );
    APP_ERROR_CHECK(nrf_drv_spis_buffers_set( &spis, spis_txBuf, spis_txLlength, spis_rxBuf, spis_rxLlength ));

In the image below the MISO is blue, the clock is green and the chip select is yellow. 
The MISO is controlled by the nRF5280 and the clock and CS are controlled by the SAM4e. The MISO is set as an input to the SAM4e with 
no pull up or pull down defined.

What we are seeing is the MISO spike high after the last bit of the MISO is clocked. Any advice?

[Håkon Alseth]

Hi,

 

The line is tristated after the csn pin goes inactive, you can add a pull-resistor on the line if you want it to be at a defined level.

Is this causing any problems in your design?

 

Kind regards,

Håkon