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Watchdog event handler timeout

I want to write some values to flash before the watchdog resets. For this I have the watchdog event handler specified:

err_code = nrf_drv_wdt_init(&config, wdt_event_handler);

In the wft_event_handler function I write a struct to flash with the fds module. This struct conaints 16 bytes, so 4 words. If I'm right the watchdog event handler takes 2*32768khz clock cycles, so around 61uS. I read somehwere that 1 words takes about 46 us. Is there a way to increase this timeout somehow? I need to write all this data to flash before a watchdog timeout occurs.

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  • Hi,

    I tested your hex file, and it works for me. See log:

    <info> app_timer: RTC: initialized.
    <info> app: Template example started.
    <info> app: Fast advertising.
    <info> app: Data from previous run:
    <info> app:  D8 9D 1A 61 CE 31 BC 7B|...a.1.{
    <info> app:  29 39 00 06 B3 4D B3 C6|)9...M..
    <info> app: Updated data:
    <info> app:  D9 9D 1A 61 CE 31 BC 7B|...a.1.{
    <info> app:  29 39 00 06 B3 4D B3 C6|)9...M..
    <info> app_timer: RTC: initialized.
    <info> app: Template example started.
    <info> app: Fast advertising.
    <info> app: Data from previous run:
    <info> app:  D9 9D 1A 61 CE 31 BC 7B|...a.1.{
    <info> app:  29 39 00 06 B3 4D B3 C6|)9...M..
    <info> app: Updated data:
    <info> app:  DA 9D 1A 61 CE 31 BC 7B|...a.1.{
    <info> app:  29 39 00 06 B3 4D B3 C6|)9...M..
    <info> app_timer: RTC: initialized.
    <info> app: Template example started.
    <info> app: Fast advertising.
    <info> app: Data from previous run:
    <info> app:  DA 9D 1A 61 CE 31 BC 7B|...a.1.{
    <info> app:  29 39 00 06 B3 4D B3 C6|)9...M..
    <info> app: Updated data:
    <info> app:  DB 9D 1A 61 CE 31 BC 7B|...a.1.{
    <info> app:  29 39 00 06 B3 4D B3 C6|)9...M..
    <info> app_timer: RTC: initialized.
    <info> app: Template example started.
    <info> app: Fast advertising.
    <info> app: Data from previous run:
    <info> app:  DB 9D 1A 61 CE 31 BC 7B|...a.1.{
    <info> app:  29 39 00 06 B3 4D B3 C6|)9...M..
    <info> app: Updated data:
    <info> app:  DC 9D 1A 61 CE 31 BC 7B|...a.1.{
    <info> app:  29 39 00 06 B3 4D B3 C6|)9...M..
    

    Perhaps the problem here is with how you reset? As mentioned, this is relying on undefined behavior and the type of reset will affect how this happens. I tested using "nrfjprog --reset", which performs a soft reset. If you for instance use a pin reset, things will be different. A watchdog reset should be similar to a soft reset in this regard. But please remember that in addition to types of reset varying there can also be variations between individual ICs etc (again, this is relying on undefined and uncharacterized behaviors).

  • Ah, that was the problem. I indeed did a pin reset, because according to this: https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52833%2Fpower.html&cp=4_1_0_4_2_5_7&anchor=concept_res_behav

    a pin reset has the same behaviour as a wdt reset, so that's why I tested with that one.

    I added a watchdog reset to my template program, and there too the RAM retaines after reset. I know you said that this is out of spec, but it seems like wdt reset in this case is same as soft reset not as hard reset.

    Anyway, I now try to implement it in my own program, at least I have it working in a template for reference.

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