nRF52833 GPIO behavior during pin reset

[Pascal Künzi]

Hi guys

Could you tell me the expected pin states while the nRF52833 is kept in reset with the pin reset?

For the nRF52840 i have found this devzone entry:

It basically states, that the pins will be configured as input disconnect.

As experienced with the nRF52832, the pins seem to be all configured as input disconnected while the pin reset is asserted.
Thus, we would have expected the same behavior on the nRF52833.

Yet, in this devzone entry of the nRF52840, following is stated:

"When reset pin is pushed the pin behavior is undefined, it may be output or floating. It is not much that can be done about this other than ensure that the pin reset is pushed for a short period of time as possible, for instance >0.2us is sufficient to ensure a hardware reset."

Having pins randomly configured as output and driving unknown circuitry seems critical.

I haven't checked the behavior on all pins but the configured UARTE TX pin is driven low for as long as the pin reset is asserted.

Do pins configured for certain peripherals lead to different pin states during a reset?

I hope you can help me clarify this.

Thank you in advance!

Regards,
Pascal

[run_ar]

Hi,

There is likely some marginal differences to when the reset signal reaches the different modules inside the chip. Because of this it's not possible to guarantee the exact behavior. It will likely depend on what is connected to the pin. After reset the pin will have the default state (input and disconnected - PIN_CNF[n]).

[Pascal Künzi]

Hi,

Thank you for the short explanation.

I did a few more tests with various peripherals and pins. Overall, the pins are either configured as input disconnected or output low. The output low configuration seems to occur, when a pin is used by an active peripheral, that uses the pin in output configuration, during the time of the pin reset. A softreset does not seem to cause this behavior.

In the table below I have added an incomplete list of peripherals that cause this behavior:

Peripheral	Pin configuration
UARTE	TXD
SPIM	MOSI, SCK
SPIS	MISO
TWIM	SDA, SCL
TWIS	SDA, SCL
GPIOTE	PSEL (any gpio)
PWM	PSEL.OUT[x] (any gpio, during active modulation)

Is there a reason why this occurs on the nRF52833 but not on the nRF52832?

From your response I don't think it is possible to solve this in firmware. Any chance this will be fixed in a future silicon revision?

Is it possible to document this behavior? I have not found any information regarding the GPIO behavior during a pin reset.

[run_ar]

Hi,
I am checking internally on what we might have on this. Will get back to you.

[Pascal Künzi]

Hi, 

I am wondering if you might have any news so far?

If not, maybe you can give me a rough estimate of when you can provide more news.

[run_ar]

Hi,
I am sorry for the late answer. The change in behavior is caused by a difference in timing. Any pad configuration can stick during the pin reset, but will be reset after pin reset.

[Pascal Künzi]

Hi,

Thank you for looking into this.

Could you also give me an answer to the two questions below.

• Any chance this will be fixed in a future silicon revision?
• Will this behavior be documented?

Depending on the connected cirtcuitry, this should at least be documented to mitigate possible problems with this behavior.

Thank you for your help!

[run_ar]

Hi,
We do not have any specific plans to change this as of now. But this might change in the future.

Still discussing if and how this should be documented. Have you made any observation that indicate that the GPIO state change to something else during reset pin low than?

1. Default reset state 
2. The current state before entering reset

[Pascal Künzi]

Hi,

Thank you for the update. I guess we have to live with that for now. Let me know, once there is more information available.

No, so far I have only observed the behaviour mentioned above.