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nRF51 patch unit (PU) and AHB Multi-Layer Interface (AMLI)

Chinook

Header for nRF51 (nrf51.h) mentions two peripheral blocks completely missing from chip documentation. Are they functioning? If so, the comment for PATCHADDR field of PU says it's relative. Is it relative to the address of patched instruction (flash word)? Concerning AMLI, do higher values of RAM priority correspond to higher RAM access priority or vice versa?

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    Hi Chinook, PU is not supported anymore. I have created a ticket to remove those from the header files. We have DFU now for firmware updates on nRF51 and on nRF52 we have FPB module on ARM Cortex-M4. More details on FPB can be found here

    Regarding RAM priority in AMLI, it is same as interrupt priority. Lower number means higher priority, i.e. 0 is highest priority.

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    Hi Chinook, PU is not supported anymore. I have created a ticket to remove those from the header files. We have DFU now for firmware updates on nRF51 and on nRF52 we have FPB module on ARM Cortex-M4. More details on FPB can be found here

    Regarding RAM priority in AMLI, it is same as interrupt priority. Lower number means higher priority, i.e. 0 is highest priority.

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