recommended chip antenna, debugger for nRF52 based design

[Lakerno]

Is there any recommended chip antenna for NRF52 SoC? Any guideline on the antenna placement, designing the matching circuit etc? I assume for NRF52, no need for an external balun, since there is one integrated. Is that correct?

For debugging code on the chip, do I need to add a Segger J-Link port on my board?? Or is there any other way? Also do I need to buy an external debugger? (for eg like the TI www.ti.com/.../cc-debugger)

[Lakerno]

Sorry I think I am a bit confused. I see that NRF52 has an internal balun and is matched to 50ohm, For matching the external chip antenna to 50 ohm, do I need to another matching Pi Network? If yes the L1 and C3 in the reference design are part of this Pi network and I need to add only a 3rd component? Or L1 and C3 and just filtering ckt and not part of the Pi network, and I need a seperate Pi network?

In both cases, how exactly do I design the Pi network to match the Antenna to 50ohm? Can I find the values of this Pi network only after I have the PCB fabricated? Or is there any way to calculate it before hand? If it can be calculated only after having the PCB back, then can just leave the footprint for components open and then solder the Pi network components back to the PCB board? How exactly to find the values of this network?

Any help will be greatly appreciated?

[Øyvind Karlsen]

Please see the update to my original answer.

[Øyvind Karlsen]

For making the Pi-network please see the whitepaper on Antenna Tuning

[EL34PP]

If i'm not completely following Nordic reference PCB layout, how to design that T-network value?

[Håkon Alseth]

It's set from our side, and we always strongly recommend to use the values and layout recommendations that we provide to ensure that the performance of your design is ideal.

If you do not follow our ref. design, you will have to use spectrum analyzer and tune the output impedance to 50 ohm, as well as suppress noise, and you will have to repeat measurement of output power and harmonics until you find a sufficient combination. A sufficient margin (what FCC/ETSI requires) in terms of the harmonics level, these shall be less than -30 dBm, ideally with a 5-10 dB margin to account for chip- and component variation. If you have not done this before, or and/do not have a spectrum analyzer, this will be a time-consuming task. Soldering skills must be above average, and you will also need to have access to various values of inductors and C0G/NP0 grade caps in 0402 size.

Cheers, Håkon