Minimize ADC Sampling power consumption

Question

I am developing my ADC sampling code for minimal power consumption. There is a timer with ppi module that generates interrupt for sampling. Please see the code below: 
 
 Can I use app_timer instead of NRF_DRV_TIMER_INSTANCE in this code to reduce overall micro power consumption? What are the other areas of the code I could change to reduce micro power consumption. 
 Please advise.

Jared · Accepted Answer

Hi there, 
 We have a low power SAADC example at our Github repo. You can find it here . Steps that are implemented for low power in the example: 
 
 Low Power -> 
 
 The low-power mode in the SAADC driver will trigger START task right before sampling, instead of when buffers are setup using nrf_drv_saadc_sample_convert(). This will enable EasyDMA only during sampling, but leave it disabled when not sampling. The EasyDMA consumes around 1.5mA when enabled. 
 Low power can only be obtained when UART is disabled. UART will add between 50-600uA current consumption, depending on TX/RX configuration. 
 Enable DCDC converter at startup with NRF_POWER->DCDCEN = 1; 
 Use RTC instead of TIMER periperal. That will save ~300uA.

regards 
 Jared

Jared · Answer

Hi, 
 
 RTC timer compare register which decides what value the counter will generate a compare event is 8 ticks. This is also the sampling interval as the RTC handler will call nrf_drv_saadc_sample(). The CC register ticks is in this example equal to RTC_US_TO_TICKS which multiples the first parameter with the second and divides it by 1000000U. 
 RTC_US_TO_TICKS( 250*1000, 32) = 8 ticks.

Kaveh.M said: Also, how can I completely disable UART. Is this by commenting out the NRF_LOG() lines? 
 Yes that works. You should also comment out the call to NRF_LOG_DEFAULT_BACKENDS_INIT() in that case. 
 regards 
 Jared

Minimize ADC Sampling power consumption

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