Can you help me check if it is right that the wires connect to the nrf52840 chips?

[lgs]

Hi Team,

I try to design a PCB based on nrf52840 chips, can you help me check if it is right?

Something like Power supplement, SPI interfaces, and debug and programming interfaces etc.

Best,

Gaosheng

[Marjeris Romero]

Hi Gaosheng,

Yes, we can help you reviewing both your schematic and layout files. To do this it's better if you share your project files. If you don't want to disclose the whole design you can open a new private ticket and share your project files there.

I also recommend to familiarize yourself with the 'Reference circuitry' section in the nRF52840 PS and try to copy the reference design and layout from it to ensure optimal performance: https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52840%2Fref_circuitry.html&cp=4_0_0_6_2

Best regards,

Marjeris

[lgs]

Hi Marjeris,

Thanks for your help! Yes, I can share the whole file with you. I didn't put the whole file, because of the big size of the screenshot. 

Best,

Gaosheng

[Marjeris Romero]

Hi,

I am so sorry but I not able to view your file. Could you make sure the file is uploaded correctly?

[lgs]

Sorry for that.

You can find the file here: drive.google.com/.../view

[Marjeris Romero]

Hi again,

I have now reviewed your schematics. I have the following comments:

• You NEED to connect XC1 and XC2 pins to a 32MHz crystal and following crystal capacitors for the chip to function, otherwise the chip will not start.
• DEC5 should be connected to a 820pF decoupling capacitor.
• If VBUS is not in use, please connect VBUS pin to ground.
• You are missing several DEC decoupling capacitors. DEC1 should be connected to a 100nF capacitor, DEC4 and DEC6 connected together and to a 1uF capacitor. Please take a look at the reference schematic for nRF52840 CKAA in the PS or in the Nordic Infocenter.
• You are also missing the decoupling capacitors in VDD_nRF (VSU in your schematics), so a 4.7uF, 1.0uF, and 2 x 100nF capacitors connected to each their VDD pin (please follow the reference design).
• ANT pin should be connected to the matching network used in the reference design (L1, C3 and L5 components) and then to the antenna of your preference.

Please try to copy the components used in the nRF52840 reference design to ensure proper performance. Optional components are marked as "optional" in the reference design. All the other components need to be present for the chip to function properly.

Best regards,

Marjeris