How to set the vdd level

[helen]

Hi

         How to set the vdd level to 3.3v when the system is in the High Voltage mode?I can't fine any api about setting vdd level in document.

[Simonr]

Hi

The output voltage from REG0 is set with the UICR_REGOUT0 register in the nrf52833_bitfields.h header file in the MDK 

/* Register: UICR_REGOUT0 */
/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */

/* Bits 2..0 : Output voltage from REG0 regulator stage. */
#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */
#define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */
#define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */
#define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */
#define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */
#define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */
#define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */

Best regards,

Simon

[helen]

Hi

        I use SES,How to set in SES,Thanks.