NRF5340 Power Consumption details

[sredaley]

We are performing a preliminary power analysis with this device and have questions regarding the power consumption reported in the Product Specification. For example, the TWIM interface is noted to draw 965 uA when transferring data. There does not appear to be any data for when the peripheral is enabled but idle. Additionally, in prior devices (nrf52832) it was known that EasyDMA contributed 1-2mA of consumption in addition to the peripheral. Is this now reported as a single compounded number? ie 965uA includes the use of EasyDMA? 

If this is the case, how would we determine the use of both TWIM and SPIM concurrently? I am trying to determine if there is any EasyDMA overhead associated with the reported current consumption numbers or if TWIM and SPIM transferring should be considered to consume nearly 2mA.

Please advise.

[Stian Røed Hafskjold]

Hi, the master peripherals do not consume any extra current when they are enabled but idle. It's only the slave peripherals that are waiting from an interrupt on the chip select pin that will consume extra current in idle.

In the nRF53 PS, under current consumption -> electrical specification, the numbers are reported as single compounded numbers, including the HF clock and the DMA current, which will be a significant part of the total current consumption. The HF clock and DMA currents do not duplicate when more than one peripheral is running, so you can't add up the reported run currents for the TWIM and SPIM. The run current for one peripheral alone is in the < 100 uA range.

[sredaley]

Does this mean that the total consumption for running a SPIM Transfer at 2Mbps is 935 uA inclusive of the Application core? 

Or is current consumption of a SPIM Transfer at 2Mbps 935 uA + IAppcpu5 3.3mA for example..

[Stian Røed Hafskjold]

Since the SPIM is using DMA the CPU is not involved during the transaction. But if the application CPU is doing something else at the same time, you will have to add the CPU current as well, to get the potential peak current. But again, the IAppcpu5 contains parts of the clock tree that is distributed to both the CPU and the SPIM, so it should be lower than 935 uA + 3.3mA. Also the current consumption of the CPU depends on what it is doing, how many wait states, how often there is a DMA write/read, etc.

[Stian Røed Hafskjold]

I should also add that in most applications the CPU (3.3mA) is mostly in idle (< 2uA). It only wakes up to do its tasks for a few µs at a time, and then goes back to idle. Of course unless you are running some very CPU intensive algorithms.