SPIS setup time before first SCK when exit low power system on mode

[Jackson Burnette]

Hello, I have a two part question with regard to SPIS setup time when exiting low power mode on an nRF52840.

We are using the SPIS peripheral on an nRF52840. General guidance I've seen (e.g., here and here) is that setup time from SCN assert to first clock should be 10us. However, the nRF52840 product specification indicates that the minimum setup time is 1us. The nRF52832 product specification, on the other hand, does break out setup time between constant latency and low power mode. It indicates that when coming out of constant latency mode the minimum setup time is 1us and for low power mode the minimum setup time is "t_{SPIS,SUCSN,CL} + t_{START_HFINT}", in other words "the setup time for constant latency mode plus the start time of the HF clock". In turn, the start time for the HF clock is indicated as a typical time of 3us (max is not given). Is this the basis for the 10us guidance for the low power mode setup time? Is the guidance applicable for an nRF52840?

Second question, is it safe to say that the 10us setup time begins when the device first come out of sleep, not necessarily when the chip select is asserted? We cannot achieve a 10us setup time from CSN to first SCK directly in hardware with our SPI master. So, we would need to work around the hardware shortcoming in firmware in order to achieve 10us from CSN to first SCK. However, we have a handshake mechanism in our spi protocol that will cause the Nordic to exit sleep before CSN is asserted. I wonder if it would be equally valid to introduce a delay such that there is at least 10us from when the device exits low power mode and when CSN is asserted, and we could use a shorter CSN to first SCK?

[Jørgen Holmefjord]

Hi,

The nRF52832 product specification, on the other hand, does break out setup time between constant latency and low power mode. It indicates that when coming out of constant latency mode the minimum setup time is 1us and for low power mode the minimum setup time is "t_{SPIS,SUCSN,CL} + t_{START_HFINT}", in other words "the setup time for constant latency mode plus the start time of the HF clock". In turn, the start time for the HF clock is indicated as a typical time of 3us (max is not given). Is this the basis for the 10us guidance for the low power mode setup time?

Yes, that is correct. It is the startup time for HFINT and startup time for SPIS that accounts for the 10 us guidance. The startup time for HFINT may vary over process, voltage, and temperature, which is why the guidance is a bit higher than the typical number from the PS.

Is the guidance applicable for an nRF52840?

Yes, the startup time should be similar for nRF52840 and nRF52832. The SPIS peripheral should also be very similar/the same design.

is it safe to say that the 10us setup time begins when the device first come out of sleep, not necessarily when the chip select is asserted?

The main contributor to the time is the startup time for HFINT. If you ensure that HFINT is available when CSN is asserted, you only need to adhere to the 1us spec in the SPIS peripheral documentation.

We cannot achieve a 10us setup time from CSN to first SCK directly in hardware with our SPI master. So, we would need to work around the hardware shortcoming in firmware in order to achieve 10us from CSN to first SCK. However, we have a handshake mechanism in our spi protocol that will cause the Nordic to exit sleep before CSN is asserted. I wonder if it would be equally valid to introduce a delay such that there is at least 10us from when the device exits low power mode and when CSN is asserted, and we could use a shorter CSN to first SCK?

If you wakeup the chip earlier, HFINT will be started when required/requested by the CPU. If you do not go back to sleep, during this period, the HFINT should be available for SPIS when needed. Then you can shorten the delay between CSN and SCK down to the specified 1us.

Best regards,
Jørgen