pipe info in nRF24L01+

[mike]

from the product spec NOTE: The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low transition. The pipe information is unreliable if the STATUS register is read during an IRQ pin high to low transition.

It has been mentioned several times in the forum to watch out for this, but the note doesn't make sense (to me). First if you mask the interrupts the IRQ will never change. What happens? Assuming the IRQs are not masked, but there are 2 messages in the RX fifo - After reading the first message at what does the pipe info in the status and length registers reflect the 2nd message, and how are you supposed to reliably read them (assuming you don't exit the interrupt routine)?

thanks mike

[Håkon Alseth]

Hi Mike,

That note points to when the IRQ pin indicates an interrupt. If in that transaction, you read the STATUS register, the bits can not be reliable. What you then do is to ensure that the IRQ pin is properly asserted before reading the STATUS-register and clearing the interrupt cause (which will return the IRQ pin to high state).

Usually, this is not an issue, as it takes some time for the application MCU to register a pin-interrupt (us-range). At this time, every thing has stabilized, and you are safe to read the STATUS register.

If you do not enable the IRQ pin, meaning that you will do a polling sequence, this should not have an effect on your status-routine.

Best regards Håkon