pipe info in nRF24L01+

[mike]

from the product spec NOTE: The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low transition. The pipe information is unreliable if the STATUS register is read during an IRQ pin high to low transition.

It has been mentioned several times in the forum to watch out for this, but the note doesn't make sense (to me). First if you mask the interrupts the IRQ will never change. What happens? Assuming the IRQs are not masked, but there are 2 messages in the RX fifo - After reading the first message at what does the pipe info in the status and length registers reflect the 2nd message, and how are you supposed to reliably read them (assuming you don't exit the interrupt routine)?

thanks mike

[mike]

Håkon,

Thank you for your reply. It seems very, very strange that the act of asserting the IRQ pin would have an effect on the STATUS register?

In my second case (what is happening in my system) is that there are multiple messages in the RX queue, so even though I am using interrupts, I read the first message and then I read the status register to see if there is another message without exiting the interrupt routine. It is entirely possible that I am reading the STATUS exactly as the second (or third) IRQ is happening, but I am already in the interrupt handling routine. Then what happens?

[Håkon Alseth]

Hi Mike,

If you have a scenario where your RX receives more interrupts while in the ISR, then you have a race condition. To handle this properly, you should check the FIFO_STATUS register to see if the RX FIFO still has entries in it (poll it). If you use ACKing, you will have at least ~150 us before the interrupt is asserted again as the PLL has 130 us turn-around time.

Note: If you fill up your RX_FIFO without reading out the payloads, then your RX will lock up until you flush the FIFO or read out at least one payload.

BR Håkon