from the product spec NOTE: The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low transition. The pipe information is unreliable if the STATUS register is read during an IRQ pin high to low transition.
It has been mentioned several times in the forum to watch out for this, but the note doesn't make sense (to me). First if you mask the interrupts the IRQ will never change. What happens? Assuming the IRQs are not masked, but there are 2 messages in the RX fifo - After reading the first message at what does the pipe info in the status and length registers reflect the 2nd message, and how are you supposed to reliably read them (assuming you don't exit the interrupt routine)?
thanks mike
