pipe info in nRF24L01+

[mike]

from the product spec NOTE: The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low transition. The pipe information is unreliable if the STATUS register is read during an IRQ pin high to low transition.

It has been mentioned several times in the forum to watch out for this, but the note doesn't make sense (to me). First if you mask the interrupts the IRQ will never change. What happens? Assuming the IRQs are not masked, but there are 2 messages in the RX fifo - After reading the first message at what does the pipe info in the status and length registers reflect the 2nd message, and how are you supposed to reliably read them (assuming you don't exit the interrupt routine)?

thanks mike

[Håkon Alseth]

Hi Mike,

That note points to when the IRQ pin indicates an interrupt. If in that transaction, you read the STATUS register, the bits can not be reliable. What you then do is to ensure that the IRQ pin is properly asserted before reading the STATUS-register and clearing the interrupt cause (which will return the IRQ pin to high state).

Usually, this is not an issue, as it takes some time for the application MCU to register a pin-interrupt (us-range). At this time, every thing has stabilized, and you are safe to read the STATUS register.

If you do not enable the IRQ pin, meaning that you will do a polling sequence, this should not have an effect on your status-routine.

Best regards Håkon

[mike]

Håkon,

Thank you for your reply. It seems very, very strange that the act of asserting the IRQ pin would have an effect on the STATUS register?

In my second case (what is happening in my system) is that there are multiple messages in the RX queue, so even though I am using interrupts, I read the first message and then I read the status register to see if there is another message without exiting the interrupt routine. It is entirely possible that I am reading the STATUS exactly as the second (or third) IRQ is happening, but I am already in the interrupt handling routine. Then what happens?

[mike]

Håkon,

I think the penny just dropped. I suspect that the answer is that the STATUS register is not double buffered and so if the info is latched in the middle of reading the STATUS register the first bits output on the SPI interface will be the old info and the last bits will be the new info.

Since the bits are transmitted MSB first, by the time the RX_DR is asserted the RX_P_NO will be valid. There does seem to be an issue with TX_FULL as in this case, when the last location is transmitted, one could read the STATUS resgister and TX_DS could be set and TX_FULL could still be set. (TX_DS new info, TX_FULL old info), but I can't imagine any situation in which this would matter.

On the other hand the note (warning) is in the product spec (and was mentioned several times in this forum by Nordic employees), so I am still a little concerned there is more to this?

thanks Mike

[Håkon Alseth]

Mike,

If this note is not fully implemented, you can be in a situation where you get corrupted info. This may give you garbage data.

You can lock up the state machine inside the radio-core if spec is not followed. An example of this is: A very important thing to always check if dynamic payload length is used, is the payload length. If you read out a payload of > 32 byte, then the state machine will go haywire and most likely lock up your receiver until power-cycle.

Best regards Håkon

[mike]

Håkon,

I understand the warning about the payload > 32.

My point was "fully implementing" the note about the STATUS register, which I can't do if I don't understand it.

mike