QSPI Not waking from deep sleep on startup

[edmcnicholas]

In SDK 1.9.0 i saw that QSPI deep power down was implemented and i can confirm that that works using the below code.  The issue I see is that if the device is in deep power down mode and then the device is rebooted and power is maintained in my case through the debugger the device does not reinitialize so this kind of defeats the use of power management.   I also see that the call to get device binding returns a 0 so I can not make a call to run a resume action.

Previous to this I was using the device as SPI NOR and it restarted just fine.  I see that when powered down my board is running at the same power level with both drivers idle.  Is this the wrong code or am I missing something?  I see that dpd is only implemented in the nrf_qspi_nor.c qspi_nor_pm_action function.

Thanks

Ed

#if (CONFIG_NORDIC_QSPI_NOR - 0) || DT_NODE_HAS_STATUS(DT_INST(0, nordic_qspi_nor), okay)
g_qspi_dev = device_get_binding(DT_LABEL(DT_INST(0, nordic_qspi_nor)));
#endif

pm_device_action_run(g_qspi_dev,PM_DEVICE_ACTION_SUSPEND);

[edmcnicholas]

To my knowledge all other devices need the AB command to return from DPD so it seems like maxtronix is the outlier.

new maxtronix chipset

8.22 ENTER DEEP POWER DOWN (DP, B9h) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter into Power-down mode). During this mode, standby current is reduced from Isb1 to Isb2. While in the Power-down mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated by driving the CE# pin low and shifting the instruction code into the device. The CE# pin must be driven high after the instruction has been latched, or Power-down mode will not engage. Once CE# pin driven high, the Power-down mode will be entered within the time duration of tDP. While in the Power-down mode only the Release from Powerdown/RDID instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored, including the Read Status Register instruction which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. It is available in both SPI and QPI mode

I found the same in cypress memory

4.3.5 Interface Standby When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface waits for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes low to begin a new command. While in interface standby state the memory device draws standby current (ISB) if no embedded algorithm is in progress. If an embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to standby current draw. A Deep Power Down (DPD) mode is supported by the FS-S Family devices. If the device has been placed in DPD mode by the DPD (B9h) command, the interface standby current is (IDPD). The DPD command is accepted only while the device is not performing an embedded algorithm as indicated by the Status Register-1 volatile Write In Progress (WIP) bit being cleared to zero (SR1V[0] = 0). While in DPD mode the device ignores all commands except the Release from DPD (RES ABh) command, that will return the device to the Interface Standby state after a delay of tRES.

Giga memory

7.21. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the
Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active
use, since in this mode, the device ignores all Write, Program and Erase commands.
Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in
progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by
executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands
are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command or software reset command.
The Release from Deep Power-Down and Read Device ID (RDI) command releases the device from Deep power-Down
mode , also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-Up.
The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS# goes high.
The command sequence is shown below. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a
delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-
Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.

ISSI

8.22 ENTER DEEP POWER DOWN (DP, B9h) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter into Power-down mode). During this mode, standby current is reduced from Isb1 to Isb2. While in the Power-down mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated by driving the CE# pin low and shifting the instruction code into the device. The CE# pin must be driven high after the instruction has been latched, or Power-down mode will not engage. Once CE# pin driven high, the Power-down mode will be entered within the time duration of tDP. While in the Power-down mode only the Release from Powerdown/RDID instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored, including the Read Status Register instruction which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. It is available in both SPI and QPI mode

[edmcnicholas]

After searching code please refer to  1.9.0\zephyr\drivers\flash\spi_nor.c for the proper implementation.  In their code they issue a return from DPD on init. 

This is how the qspi should be implemented.  Ideally there would also be an idle in standby like the spi nor code as well. 

function "static int spi_nor_configure(const struct device *dev)" line 1031.  

[edmcnicholas]

The implimentation for idle in dpd would be found in lines 463 to 497

[edmcnicholas]

so are you going to put in a ticket to fix this in an upcoming release?  The current driver is not in line with standard QSPI ics.

[ovrebekk]

Hi Ed

Sorry for the slow response, I was on travel all last week. 

I have asked the developers for some input on your findings, and will try to get back to you in a day or two. 

Best regards
Torbjørn