nrf52833 pad sizes and layout

[David Guest]

I have loaded up the altium design and can see the pad and via sizes used.

The drill size for the in pad via is very small (0.15mm) which will increase pcb costs and also reliability.

Also he pad size could be increased to improve the annulus.

Has any tried with large drill sizes and possible a larger pad with increased solder resist expansion (solder resist defined pad size) ?

[David Guest]

Thankyou that was very helpful.

Another question the used pins on the nRF52840  that are NCs on the nRF52833 - are they truly not connected. I noticed that you routed through unused pins to connect the reset pin on the Dongle design, I wondered if this is  still ok for nRF52833

[Bendik Heiskel]

Yes, the pins labeled NC on the nRF52833 are not physically connected internally so routing through them are OK.

 

Best regards,

Bendik

[David Guest]

Thanks again. 

Not specifically related to this, but I have a question re pin allocation for internal modules (SPI, UART,I2C etc).

Can any of the IO pins be allocated randomly aor is a grouping required. My interntion is to group in layout signal groups (SCK,MOSI,,MISO,CS) which might result in an eractic selection of IO ports  (avoiding using the 10KHz recommend ones for the serial buses).

Does this cause a problem - this is my first usage of the devices so I am not familiar with the IO mapping contraints - if any.

[Bendik Heiskel]

Any pins can be used for the internal peripherals, with the exceptions of the low frequency pins which cant be used for signals over 10 kHz as you mentioned. Keep in mind that if SPIM0, SPIM1 or SPIM3 is used with 8Mbps data rate, its recommended to use P0.04, P0.31 or P1.09 for the clock signal.

[David Guest]

Thankyou again for your prompt answer - very helpful