The Cortex-M4 exception handling and NVIC support late-arriving exceptions as discussed for example in the Cortex-M4 Generic User Guide. In this regard, my question is: What is the minimum entry latency (i.e., best-case) of a late-arriving exception?
Background: For tail-chaining the Cortex-M4 Technical Reference Manual states "Tail chaining requires six cycles when using zero wait state memory", but it says nothing about late arrival. I found the following article in the ARM knowledge base: https://developer.arm.com/documentation/ka001190/latest. There I read "...the interrupt latency [...] might be less than the standard interrupt latency for the particular processor and system. Some (but not all) Cortex-M processors provide an implementation-time option for the chip designer to specify a minimum value for the interrupt latency, reducing or removing the uncertainty in interrupt latency by adding stall cycles in such cases. Documentation of the specific chip should provide details of this setting, if applicable." Unfortunately, I found nothing about that in the nRF Product Spec.
