I currently have an issue where by the Chip-Select is not toggled at all when configuring the csn pin to pin <18> on the Nrf52840 using Zephyr (version 2.7.1).
See dts configuration (zephyr.dts) with P0.18 as Chip Select below:
qspi: qspi@40029000 {
compatible = "nordic,nrf-qspi";
#address-cells = < 0x1 >;
#size-cells = < 0x0 >;
reg = < 0x40029000 0x1000 >;
interrupts = < 0x29 0x1 >;
status = "okay";
label = "QSPI";
sck-pin = < 0x13 >;
io-pins = < 0x15 >, < 0x16 >;
csn-pins = < 0x12 >;
mx25l1606: mx25l1606e@0 {
status = "okay";
compatible = "nordic,qspi-nor";
reg = < 0x0 >;
writeoc = "pp";
readoc = "fastread";
sck-frequency = < 0xf42400 >;
label = "MX25L1606E";
jedec-id = [ C2 20 15 ];
sck-delay = < 0x1 >;
sfdp-bfp = [ E5 20 F1 FF FF FF 7F 00 44 EB 08 6B 08 3B 04 BB EE FF FF FF FF FF 00 FF FF FF 00 FF 0C 20 0F 52 10 D8 00 FF 23 72 F5 00 82 ED 04 B7 44 83 38 44 30 B0 30 B0 F7 C4 D5 5C 00 BE 29 FF F0 D0 FF FF ];
size = < 0x200000 >;
has-dpd;
t-enter-dpd = < 0x2710 >;
t-exit-dpd = < 0x88b8 >;
};
};
See dts configuration (zephyr.dts) with P1.05 as Chip Select below:
qspi: qspi@40029000 {
compatible = "nordic,nrf-qspi";
#address-cells = < 0x1 >;
#size-cells = < 0x0 >;
reg = < 0x40029000 0x1000 >;
interrupts = < 0x29 0x1 >;
status = "okay";
label = "QSPI";
sck-pin = < 0x13 >;
io-pins = < 0x15 >, < 0x16 >;
csn-pins = < 0x25 >;
mx25l1606: mx25l1606e@0 {
status = "okay";
compatible = "nordic,qspi-nor";
reg = < 0x0 >;
writeoc = "pp";
readoc = "fastread";
sck-frequency = < 0xf42400 >;
label = "MX25L1606E";
jedec-id = [ C2 20 15 ];
sck-delay = < 0x1 >;
sfdp-bfp = [ E5 20 F1 FF FF FF 7F 00 44 EB 08 6B 08 3B 04 BB EE FF FF FF FF FF 00 FF FF FF 00 FF 0C 20 0F 52 10 D8 00 FF 23 72 F5 00 82 ED 04 B7 44 83 38 44 30 B0 30 B0 F7 C4 D5 5C 00 BE 29 FF F0 D0 FF FF ];
size = < 0x200000 >;
has-dpd;
t-enter-dpd = < 0x2710 >;
t-exit-dpd = < 0x88b8 >;
};
};
Searching the zephyr.dts file for any instances of '0x12' shows no GPIO pin conflicts. And using a nrfx implementation using the same pin works correctly.
Zephyr generated nrfx_qspi_config_t struct:QSPIconfig nrfx_qspi_config_t {...}
xip_offset uint32_t 0
pins nrf_qspi_pins_t {...}
sck_pin uint8_t 19 '\023'
csn_pin uint8_t 18 '\022'
io0_pin uint8_t 21 '\025'
io1_pin uint8_t 22 '\026'
io2_pin uint8_t 255 'ÿ'
io3_pin uint8_t 255 'ÿ'
prot_if nrf_qspi_prot_conf_t {...}
readoc nrf_qspi_readoc_t NRF_QSPI_READOC_FASTREAD
writeoc nrf_qspi_writeoc_t NRF_QSPI_WRITEOC_PP
addrmode nrf_qspi_addrmode_t NRF_QSPI_ADDRMODE_24BIT
dpmconfig _Bool false
phy_if nrf_qspi_phy_conf_t {...}
sck_delay uint8_t 1 '\001'
dpmen _Bool false
spi_mode nrf_qspi_spi_mode_t NRF_QSPI_MODE_0
sck_freq nrf_qspi_frequency_t NRF_QSPI_FREQ_DIV2
irq_priority uint8_t 0 '\0'
in-house nrfx_qspi_config_t struct:qspiConfig nrfx_qspi_config_t {...}
xip_offset uint32_t 0
pins nrf_qspi_pins_t {...}
sck_pin uint8_t 19 '\023'
csn_pin uint8_t 18 '\022'
io0_pin uint8_t 21 '\025'
io1_pin uint8_t 22 '\026'
io2_pin uint8_t 255 'ÿ'
io3_pin uint8_t 255 'ÿ'
prot_if nrf_qspi_prot_conf_t {...}
readoc nrf_qspi_readoc_t NRF_QSPI_READOC_FASTREAD
writeoc nrf_qspi_writeoc_t NRF_QSPI_WRITEOC_PP
addrmode nrf_qspi_addrmode_t NRF_QSPI_ADDRMODE_24BIT
dpmconfig _Bool false
phy_if nrf_qspi_phy_conf_t {...}
sck_delay uint8_t 1 '\001'
dpmen _Bool false
spi_mode nrf_qspi_spi_mode_t NRF_QSPI_MODE_0
sck_freq nrf_qspi_frequency_t NRF_QSPI_FREQ_32MDIV2
irq_priority uint8_t 7 '\a'
Am I missing any other configuration that should be made?
