Hi All.
I am checking battery autonomy with different settings in my Module (with an nRF52840 SoC inside) since, in my project, this is a critical restraint.
I am feeding my Module at 3V from an I-Lithium battery connected to the Vbat pin of an nPM1100-EK PMIC. Then, coming out from its VOUTB pin and protecting my battery from UVLO with a PMC.
When the charging cycle ends, I understand that the SYSREG prevents leaks from Vint to Vbus, and only CHARGER and BUCK DC-DC remain operative. Then, If you remove the load from VOUTB, you should expect the CHARGER and BUCK Regulator quiescent currents to come out from the battery, up to less than 800 nA.
But in my case, with the battery fully charged and no load in VOUTB (or VSYS), I consistently measure 3,6 mA coming out from the battery, plus around 2 mA if I connect my Module to VOUTB. No need to say that; of course, I did measure many times and even tried with a bright new nPM1100, with no changes.
This problem heavily affects my Project Autonomy, and I do not know how to get rid of it.
Any suggestion would be appreciated.
Thanks
Juan
