Pull-up circuit on nReset (P0.21) malfunctioning?

[Konrad Hammel]

We have a product that uses an nrf52832 module (vendor listed on the 3rd part modules list) and have shipped ~30,000 units using the current circuit design.  We are using SDK 14.2 and SD v5.1.0.

The product uses the P0.21 reset pin;  the pin is connected to a 10k pull-up resistor connected to Vdd and a 100nF capacitor to ground.

In our last production run we have found a number of samples (~1% at this time) that appear to be stuck in the P0.21 reset state.  These devices were working normally, for months in some cases, but are now stuck in reset across power cycles.

Measuring the voltage on P0.21 shows different values per sample but the samples that are stuck show a voltage below 2.3V (3.4V is our VDD).  We have also isolated a number of samples that show a P0.21 voltage between 2.3V and VDD that are functioning but showing an elevated current draw.

I used hot-air gun to remove the pull-up resistor on one sample that was stuck.  After measuring the resistance and  soldering the pull-up resistor again (using hot-air) the device is no longer stuck in reset and P0.21 shows a voltage of ~VDD

On another sample that was stuck in reset, metal tweezers were used to short the pull-up resistor to VDD.  This sample now works normally across power cycles as well.

Any suggestion on what the cause of this problem may be?  Any hardware or SDK erratas that might apply?

[hmolesworth]

If the 100nF capacitor to Gnd has become leaky then the use of a hot-air gun close by to remove and replace the pull-up resistor may indicate that moisture absorption or other contamination of the capacitor may be an issue. Both hot-air (very likely) and increased current through the leak (tweezer short) (less likely) can affect this. Perhaps try removing the reset pin capacitor on all the problem boards and see how many recover. That reset capacitor is not necessary, unless there are very high levels of radiated or coupled noise, which is unlikely without other issues arising. Moisture or leakage on the pull-up would be irrelevant, and the pull-up is not really required given the internal pull-up enabled when the pin is used as a reset pin. Baking a faulty board is another test which would indicate contamination should the board recover.

A leaky internal schottky protection diode to Gnd could also be an issue - caused by an ESD event - but in that case the two steps noted above would not correct the problem as the schottky leak would likely be permanent.

2.3 is 70% of 3.4, ie the switching threshold of the internal FET; a failed gate could do this, but that would not recover as in the two steps noted above.

Nordic engineers will help with errata (known and unreported), I am not aware of anything specific other than it has been reported that malfunctioning firmware can drive a reset pin low leading to permanent reset oscillation (I have not tested this). Maybe see nreset-pin-specifications.

Having a reset pin enabled adds another single-point failure mode; unless the pin is required for (say) an external watchdog chip I would recommend disabling the reset pin (requires flash erase) and removing the CR on the pin.

Edit: "but are now stuck in reset across power cycles" - it is possible to have a latch-up condition where a parasitic thyristor-like effect prevents normal operation, typically this can only be removed by a complete removal of power (including full discharge of capacitance on port and supply pins). How long is power removed in the power-cycle mentioned above? Does a 1-minute removal of power make any difference?