Reasoning behind nrf51-pwm-library implementation

[FormerMember]

Greetings,

Kudos for implementing a no glitch version of PWM with and without using timeslot.

github.com/.../nrf_pwm_noglitch.c.

Could the reasoning for the following be explained with the above PWM driver:

• Why is pwm_max_value and pwm_value multiplied by 2 used for the timer instead of just these values?
• Disabling of the PPI channels done in the IRQ routine? Could waiting for 1.5 or 2 times the PWM cycle work?

Also does this implementation have the infamous bug of the polarity inverting at times as mentioned in other posts in this forum? Thanks!

[Stefan Birnir Sverrisson]

Hi

Not yet sure about the two first questions that you ask. For your last question, this thread provides some reasoning for why the signal would flip and how to avoid it.

[FormerMember]

Thanks! This helps clear some stuff up. I'm looking for PWM for a max value of 1023 and with no prescalar of TIMER. This would result in ~15 kHz freq of PWM signal, but with the multiplication of 2 (question 1), the PWM freq reduces to ~7 kHz. Since the PWM freq is still below 64kHz limit mentioned in the link you sent, what is the reason that this is done?

I have changed the code where the multiplying by 2 is not done and the PWM gets messed up. I still can't get my head around why though.