#include <zephyr/zephyr.h>
#include <nrfx_spim.h>
#define CS_PIN 16 /* P0.16 */
#define SCK_PIN 19 /* P0.19 */
#define DC_PIN 20 /* P0.20 */
#define MOSI_PIN 32 /* P1.0 */
typedef uint8_t BYTE;
BYTE tx_buffer[5] = { 0xAF, 0x01, 0xFF, 0x01, 0x01 }; // Random test data to probe
static void spim_init(uint32_t sck_pin, uint32_t mosi_pin, uint32_t cs_pin, uint32_t dc_pin) {
nrf_spim_pins_set(NRF_SPIM3, sck_pin, mosi_pin, NRF_SPIM_PIN_NOT_CONNECTED);
nrf_spim_dcx_pin_set(NRF_SPIM3, dc_pin);
nrf_spim_dcx_cnt_set(NRF_SPIM3, 1);
nrf_spim_configure(NRF_SPIM3, NRF_SPIM_MODE_2, NRF_SPIM_BIT_ORDER_MSB_FIRST);
nrf_spim_csn_configure(NRF_SPIM3, CS_PIN, NRF_SPIM_CSN_POL_LOW, 0);
nrf_spim_frequency_set(NRF_SPIM3, NRF_SPIM_FREQ_2M);
nrf_spim_int_enable(NRF_SPIM3, NRF_SPIM_INT_ENDTX_MASK);
nrf_spim_enable(NRF_SPIM3);
}
static void sendTest() {
nrf_spim_tx_buffer_set(NRF_SPIM3, tx_buffer, 5);
nrf_spim_rx_buffer_set(NRF_SPIM3, NULL, 0);
nrf_spim_task_trigger(NRF_SPIM3, NRF_SPIM_TASK_START);
nrf_spim_event_clear(NRF_SPIM3, NRF_SPIM_EVENT_ENDTX);
}
int init_SSD1333_display() {
spim_init(SCK_PIN, MOSI_PIN, CS_PIN, DC_PIN);
sendTest();
}EDIT:
nrf_spim_disable(NRF_SPIM3);
#define CS_PIN 40 /* P1.08 */ #define SCK_PIN 5 /* P0.05 */ #define DC_PIN 30 /* P0.30 */ #define MOSI_PIN 32 /* P1.0 */