Private Peripheral Bus documentation?

[Andrew Lentvorski]

I'm trying to track down an intermittent bug in programming our Nordic board. So, I'm having to laboriously reconstruct the SWD transactions and understand them.

A transaction that occurs is "D1 OK 0F B7 99 97".

That's an AP Write access to Address 0x04. The TAR (Target Address register).

This sets the MEM-AP target address to what appears to be 0xE000EDF0 if I'm calculating correctly.

That's in a space of memory marked "Private Peripheral Bus". Where is the documentation about that space?

Thanks.

The context of this is that this is halting the processor. The transactions around this are:

81  OK  C0 00 00 00  P0  --  Write to DAPABORT and STKCMPCLR
8D  OK  00 00 00 00  P0  --  Write 0x0 to AP-select, Ap-bank, DP-BANK
 
D1  OK  0F B7 00 07  P1  --  Set MEM-AP target address to 0xE000EDF0

C5  OK  48 00 00 C5  P1  --  Write to MEM-AP CSW
F9  OK  00 00 00 00  P0  --  Read MEM-AP Data
BD  OK  C0 00 C0 00  P0  --  Actually read the data from RDBUFF

[RK]

The documentation about that is in the ARMv6M manual, it's the mandated address for the Debug Control Block, specifically the Debug Halting Control and Status Register. Writes to that are often used to halt the processor as part of the programming process.

[Andrew Lentvorski]

Thanks for the pointer. Yet another manual to RTFM.