nRf52832 CIAA reference layout

[Francesco_M]

Hello,

I noted that in the reference layout for nRF52832 CIAA with DC/DC converter there are VIP (Via-In-Pad) and blind via underneath the WLCSP package. I would like to know why you used a blind via from top layer to inner layer 1 to routing some nets connected to some pins for nRF52832 inside inner 1. Which are the drawbacks to use these vias from top to bottom and isolate them (obviously) in the inner 2 and bottom layers? In this manner we certainly have a ground planes (in bottom layer and inner2 layer) not completely filled with copper but with some vias isolated underneath the WLCSP package but I do not think that this could lead RF poor performances. Many Thanks and Best Regards.

[Kaja]

Hi,

I will try to answer you:

would like to know why you used a blind via from top layer to inner layer 1 to routing some nets connected to some pins for nRF52832 inside inner 1.

We do this to route out all the GPIO's, so that all of them can be used.

Which are the drawbacks to use these vias from top to bottom and isolate them (obviously) in the inner 2 and bottom layers?

If I understand you correctly: This vias goes from top layer to mid-layer 1, because of the size of the via. The size is small, to fit the pad and room we have, and the aspect ratio then sets the restricitons for hole depth.

Best regards,
Kaja