AoA IQ Data soundness

Hi, I'm currently using the Direction Finding Connectionless examples to evaluate using the nRF5340 for numerous projects we have lined up, and I'm having difficulty ascertaining whether or not I'm actually collecting valuable data.

I've made minimal changes to the example, just set up the GPIO overlay to match the antenna array we are using and setting up a very basic switching sequence.

My overlay file is currently set to use 3 antenna, with 0x3 set as the reference antenna.

	dfe-antenna-num = <3>;
	dfe-pdu-antenna = <0x3>;

My switching sequence is then set to {0x5,0x9}.

My understanding then is that of the 45 samples I receive from the CTE, the first 8 would be using ANT 0x3, allowing me to ascertain a reference phase using arctan2(Q,I), then the remaining would alternate between ANT0x5 and ANT0x9. From the switching samples I calculate a phase offset and use the basic θ = arccos((ψλ)/(2πd)) formula to calculate an angle.

My first 2 most basic questions are so:

1. Obviously, this approach is going to struggle with noise and reflections etc, but I'm unsure as to how big those effects might be - how flakey I should expect this naive appraoch to be. 

2.  The IQ samples themselves, I'm unsure as to what range of values I should be expecting. In most of my testing so far the majority of my samples are in the range 0±50, which from looking around on this site seems to be low.

I'm reasonably confident the data I've collected so far is garbage, and will have more equipment available soon to properly interogate my hardware setup (WFH introduces some unfortunate delays at times), but I want to check it's not my analysis of the data that's the issue.

When calculating the reference phase, I use atan(Q,I) and see that odd samples are consistently ~180° out of phase with even samples. Is this expected behaviour, and if not how am supposed to ascertain the reference phase, are there supposed to be two reference phases for odd an even sample slots? My intuition is no but as I'm sure is obvious, I'm very much learning on the job here.

Parents
  • Hi Simon, thank for your reply.

    I understand the function of the guard and reference periods, my confusion lies with exactly how the NCS direction_finding_connectionless_rx example assigns antenna patterns for these periods. The demo is highly obfuscated as it makes heavy use of HCI RPMsg calls to do most of the interfacing with the radio registers. Because of that I can't determine what data it uses to perform the first two writes to the SWITCHPATTERN  register, whether this comes from the first two entries in the ant_patterns array or whether it uses the 'PDU' antenna pattern provided in the .overlay file. If this is the wrong place to ask for specific technical details about the NCS sdk I apologise.

    My other main question in the opening post was regarding the expected range of IQ values. While the technical documention provides information on what size of information can fit in the DMA registers used to store the IQ values, I haven't been able to find information on what range I should expect "good" IQ values to fit within. Any information you could provide on this would be invaluable.

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  • Hi Simon, thank for your reply.

    I understand the function of the guard and reference periods, my confusion lies with exactly how the NCS direction_finding_connectionless_rx example assigns antenna patterns for these periods. The demo is highly obfuscated as it makes heavy use of HCI RPMsg calls to do most of the interfacing with the radio registers. Because of that I can't determine what data it uses to perform the first two writes to the SWITCHPATTERN  register, whether this comes from the first two entries in the ant_patterns array or whether it uses the 'PDU' antenna pattern provided in the .overlay file. If this is the wrong place to ask for specific technical details about the NCS sdk I apologise.

    My other main question in the opening post was regarding the expected range of IQ values. While the technical documention provides information on what size of information can fit in the DMA registers used to store the IQ values, I haven't been able to find information on what range I should expect "good" IQ values to fit within. Any information you could provide on this would be invaluable.

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