Store variables in flash at compile time

Hello I am using I am NRF SDK version 1.8.0 and nrf-zephyr v2.7.0-ncs1 (If a soultion exists on newer a rev, willing to upgrade now, otherwise it will happen some time in the future)
and I am looking for a good way to store factory settings on nrf9160 devices. 

I figured I'd make a separate storage partition that would be read only to the application and would be populated at compile time. 


I did find this support post:
How to store constant variables at specific address during compile time

Though the post is 6 years old now, and I'm wondering if there is perhaps a better way to do this using using ncs and wests tools
(should direct this more towards zephyr dev community?)
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  • Sorry for the late reply (probably shouldnt have asked before going on vacation).

    I looked the PM before a little bit, also, and hopefully made it clear to myself.
    To check:
    By default the $BUILD_DIR/partitions.yml for nrf9160 has EMPTY_0, -1 and -2, which look like prime real-estate for me.

    EMPTY_0:
      address: 0xc000
      end_address: 0x10000
      placement:
        before:
        - mcuboot_pad
      region: flash_primary
      size: 0x4000
    EMPTY_1:
      address: 0xfe000
      end_address: 0x100000
      placement:
        after:
        - littlefs_storage
      region: flash_primary
      size: 0x2000
    EMPTY_2:
      address: 0xf0000
      end_address: 0xf8000
      placement:
        after:
        - mcuboot_secondary
      region: flash_primary
      size: 0x8000
    app:
      address: 0x20200
      end_address: 0x80000
      region: flash_primary
      size: 0x5fe00
    littlefs_storage:
      address: 0xf8000
      end_address: 0xfe000
      placement:
        align:
          start: 0x8000
        before:
        - end
      region: flash_primary
      size: 0x6000
    mcuboot:
      address: 0x0
      end_address: 0xc000
      placement:
        before:
        - mcuboot_primary
      region: flash_primary
      size: 0xc000
    mcuboot_pad:
      address: 0x10000
      end_address: 0x10200
      placement:
        align:
          start: 0x8000
        before:
        - mcuboot_primary_app
      region: flash_primary
      size: 0x200
    mcuboot_primary:
      address: 0x10000
      end_address: 0x80000
      orig_span: &id001
      - mcuboot_pad
      - spm
      - app
      region: flash_primary
      sharers: 0x1
      size: 0x70000
      span: *id001
    mcuboot_primary_app:
      address: 0x10200
      end_address: 0x80000
      orig_span: &id002
      - app
      - spm
      region: flash_primary
      size: 0x6fe00
      span: *id002
    mcuboot_secondary:
      address: 0x80000
      end_address: 0xf0000
      placement:
        after:
        - mcuboot_primary
        align:
          start: 0x8000
      region: flash_primary
      share_size:
      - mcuboot_primary
      size: 0x70000
    nrf_modem_lib_ctrl:
      address: 0x20010000
      end_address: 0x200104e8
      inside:
      - sram_nonsecure
      placement:
        after:
        - spm_sram
        - start
      region: sram_primary
      size: 0x4e8
    nrf_modem_lib_rx:
      address: 0x200124e8
      end_address: 0x200144e8
      inside:
      - sram_nonsecure
      placement:
        after:
        - nrf_modem_lib_tx
      region: sram_primary
      size: 0x2000
    nrf_modem_lib_sram:
      address: 0x20010000
      end_address: 0x200144e8
      orig_span: &id003
      - nrf_modem_lib_ctrl
      - nrf_modem_lib_tx
      - nrf_modem_lib_rx
      region: sram_primary
      size: 0x44e8
      span: *id003
    nrf_modem_lib_tx:
      address: 0x200104e8
      end_address: 0x200124e8
      inside:
      - sram_nonsecure
      placement:
        after:
        - nrf_modem_lib_ctrl
      region: sram_primary
      size: 0x2000
    otp:
      address: 0xff8108
      end_address: 0xff83fc
      region: otp
      size: 0x2f4
    spm:
      address: 0x10200
      end_address: 0x20200
      inside:
      - mcuboot_primary_app
      placement:
        before:
        - app
      region: flash_primary
      size: 0x10000
    spm_sram:
      address: 0x20000000
      end_address: 0x20010000
      inside:
      - sram_secure
      placement:
        after:
        - start
      region: sram_primary
      size: 0x10000
    sram_nonsecure:
      address: 0x20010000
      end_address: 0x20040000
      orig_span: &id004
      - sram_primary
      - nrf_modem_lib_ctrl
      - nrf_modem_lib_tx
      - nrf_modem_lib_rx
      region: sram_primary
      size: 0x30000
      span: *id004
    sram_primary:
      address: 0x200144e8
      end_address: 0x20040000
      region: sram_primary
      size: 0x2bb18
    sram_secure:
      address: 0x20000000
      end_address: 0x20010000
      orig_span: &id005
      - spm_sram
      region: sram_primary
      size: 0x10000
      span: *id005
    


    Changing for example empty_1 to my setting area
    pm_static.yml:
    EMPTY_0:
      address: 0xc000
      end_address: 0x10000
      placement:
        before:
        - mcuboot_pad
      region: flash_primary
      size: 0x4000
    EMPTY_1:
      address: 0xf0000
      end_address: 0xf8000
      placement:
        after:
        - mcuboot_secondary
      region: flash_primary
      size: 0x8000
    settings:
      address: 0xfe000
      end_address: 0x100000
      placement:
        after:
        - littlefs_storage
      region: flash_primary
      size: 0x2000
    app:
    ...
    ...
    ...

    Should be ok?

    Though Im confused about the dts definitions still.
    Do I have to change them for my board?
    The generated .yml and the dts dont quite add up, or is it OK to leave it as is?
     
    &flash0 {
    
    	partitions {
    		compatible = "fixed-partitions";
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		boot_partition: partition@0 {
    			label = "mcuboot";
    			reg = <0x00000000 0x10000>;
    		};
    		slot0_partition: partition@10000 {
    			label = "image-0";
    		};
    		slot0_ns_partition: partition@50000 {
    			label = "image-0-nonsecure";
    		};
    		slot1_partition: partition@80000 {
    			label = "image-1";
    		};
    		slot1_ns_partition: partition@c0000 {
    			label = "image-1-nonsecure";
    		};
    		scratch_partition: partition@f0000 {
    			label = "image-scratch";
    			reg = <0x000f0000 0xa000>;
    		};
    		storage_partition: partition@fa000 {
    			label = "storage";
    			reg = <0x000fa000 0x00006000>;
    		};
    	};
    };

  • Hopefully i've been moving in the right direction.
    I modified my boards dts as:

    		storage_partition: partition@fa000 {
    			label = "storage";
    			reg = <0x000fa000 0x00004000>;
    		};
    
    		settings_partition: partition@fe000 {
    			label = "settings";
    			reg = <0x000fe000 0x00002000>;
    		};


    And based on /samples/application_development/code_relocation_nocopy/ 
    I've been trying to move it to my defined partition but to no avail.

    In my cmakelist I added the code relocate as:
        target_sources(app PRIVATE ${app_sources})
        target_sources_ifdef(true app PRIVATE linker_arm_nocopy.ld)
        zephyr_code_relocate(src/hw_settings.c EXTFLASH) # move settings to correct partition


    I copied the linker code from <arch/arm/aarch32/cortex_m/scripts/linker.ld> to linker_arm_nocopy:
    /*
     * Copyright (c) 2013-2014 Wind River Systems, Inc.
     *
     * SPDX-License-Identifier: Apache-2.0
     */
    
    /**
     * @file
     * @brief Linker command/script file
     *
     * Linker script for the Cortex-M platforms.
     */
    
    #include <autoconf.h>
    #include <linker/sections.h>
    #include <devicetree.h>
    
    #include <linker/devicetree_regions.h>
    #include <linker/linker-defs.h>
    #include <linker/linker-tool.h>
    
    /* physical address of RAM */
    #ifdef CONFIG_XIP
    #define ROMABLE_REGION FLASH
    #define RAMABLE_REGION SRAM
    #else
    #define ROMABLE_REGION SRAM
    #define RAMABLE_REGION SRAM
    #endif
    
    #if USE_PARTITION_MANAGER
    
    #include <pm_config.h>
    
    #ifdef LINK_INTO_s1
    /* We are linking against S1, create symbol containing the flash ID of S0.
     * This is used when writing code operating on the "other" slot.
     */
    _image_1_primary_slot_id = PM_S0_ID;
    
    #define ROM_ADDR PM_ADDRESS + PM_S1_ADDRESS - PM_S0_ADDRESS
    
    #else /* ! LINK_INTO_s1 */
    
    #ifdef PM_S1_ID
    /* We are linking against S0, create symbol containing the flash ID of S1.
     * This is used when writing code operating on the "other" slot.
     */
    _image_1_primary_slot_id = PM_S1_ID;
    #endif /* PM_S1_ID */
    
    #define ROM_ADDR PM_ADDRESS
    #endif /* LINK_MCUBOOT_INTO_s1 */
    #define ROM_SIZE PM_SIZE
    
    #define RAM_SIZE PM_SRAM_SIZE
    #define RAM_ADDR PM_SRAM_ADDRESS
    
    #else /* ! USE_PARTITION_MANAGER */
    
    #if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
    #define ROM_ADDR RAM_ADDR
    #else
    #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
    #endif
    
    #if CONFIG_FLASH_LOAD_SIZE > 0
    #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE
    #else
    #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)
    #endif
    
    #if defined(CONFIG_XIP)
    #if defined(CONFIG_IS_BOOTLOADER)
    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \
    	(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
    #else
    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)
    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
    #endif
    #else
    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
    #endif
    
    #endif /* USE_PARTITION_MANAGER */
    
    #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)
    #define CCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ccm))
    #define CCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ccm))
    #endif
    
    #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
    #define ITCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_itcm))
    #define ITCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_itcm))
    #endif
    
    #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
    #define DTCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))
    #define DTCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))
    #endif
    
    #if defined(CONFIG_CUSTOM_SECTION_ALIGN)
    _region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;
    #else
    /* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
     * to make linker section alignment comply with MPU granularity.
     */
    #if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
    _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
    #else
    /* If building without MPU support, use default 4-byte alignment. */
    _region_min_align = 4;
    #endif
    #endif
    
    #if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
    #define MPU_ALIGN(region_size) \
        . = ALIGN(_region_min_align); \
        . = ALIGN( 1 << LOG2CEIL(region_size))
    #else
    #define MPU_ALIGN(region_size) \
        . = ALIGN(_region_min_align)
    #endif
    
    MEMORY
        {
        FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE - 0x2000
        SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
        EXTFLASH (wx) : ORIGIN = 0xfe000, LENGTH = 0x2000
    
        /* TI CCFG Registers */
        LINKER_DT_REGION_FROM_NODE(FLASH_CCFG, rwx, DT_NODELABEL(ti_ccfg_partition))
        /* Data & Instruction Tightly Coupled Memory */
        LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))
        LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))
        /* STM32 Core Coupled Memory */
        LINKER_DT_REGION_FROM_NODE(CCM, rw, DT_CHOSEN(zephyr_ccm))
        /* STM32WB IPC RAM */
        LINKER_DT_REGION_FROM_NODE(SRAM1, rw, DT_NODELABEL(sram1))
        LINKER_DT_REGION_FROM_NODE(SRAM2, rw, DT_NODELABEL(sram2))
        /* STM32 alternate RAM configurations */
        LINKER_DT_REGION_FROM_NODE(SRAM3, rw, DT_NODELABEL(sram3))
        LINKER_DT_REGION_FROM_NODE(SRAM4, rw, DT_NODELABEL(sram4))
        LINKER_DT_REGION_FROM_NODE(SDRAM1, rw, DT_NODELABEL(sdram1))
        LINKER_DT_REGION_FROM_NODE(SDRAM2, rw, DT_NODELABEL(sdram2))
        LINKER_DT_REGION_FROM_NODE(BACKUP_SRAM, rw, DT_NODELABEL(backup_sram))
        /* Used by and documented in include/linker/intlist.ld */
        IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
        }
    
    ENTRY(CONFIG_KERNEL_ENTRY)
    
    SECTIONS
        {
    
    #include <linker/rel-sections.ld>
    
        /*
         * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
         * before text section.
         */
        /DISCARD/ :
    	{
    	*(.plt)
    	}
    
        /DISCARD/ :
    	{
    	*(.iplt)
    	}
    
        GROUP_START(ROMABLE_REGION)
    
    	__rom_region_start = ROM_ADDR;
    
        SECTION_PROLOGUE(rom_start,,)
    	{
    
    /* Located in generated directory. This file is populated by calling
     * zephyr_linker_sources(ROM_START ...). This typically contains the vector
     * table and debug information.
     */
    #include <snippets-rom-start.ld>
    
    	} GROUP_LINK_IN(ROMABLE_REGION)
    
    #ifdef CONFIG_CODE_DATA_RELOCATION
    
    #include <linker_relocate.ld>
    
    #endif /* CONFIG_CODE_DATA_RELOCATION */
    
        SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
    	{
    	__text_region_start = .;
    
    #include <linker/kobject-text.ld>
    
    	*(.text)
    	*(".text.*")
    	*(".TEXT.*")
    	*(.gnu.linkonce.t.*)
    
    	/*
    	 * These are here according to 'arm-zephyr-elf-ld --verbose',
    	 * after .gnu.linkonce.t.*
    	 */
    	*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
    
    	} GROUP_LINK_IN(ROMABLE_REGION)
    
    	__text_region_end = .;
    
    #if defined (CONFIG_CPLUSPLUS)
    	SECTION_PROLOGUE(.ARM.extab,,)
    	{
    	/*
    	 * .ARM.extab section containing exception unwinding information.
    	 */
    	*(.ARM.extab* .gnu.linkonce.armextab.*)
    	} GROUP_LINK_IN(ROMABLE_REGION)
    #endif
    
    	SECTION_PROLOGUE(.ARM.exidx,,)
    	{
    	/*
    	 * This section, related to stack and exception unwinding, is placed
    	 * explicitly to prevent it from being shared between multiple regions.
    	 * It  must be defined for gcc to support 64-bit math and avoid
    	 * section overlap.
    	 */
    	__exidx_start = .;
    #if defined (__GCC_LINKER_CMD__)
    	*(.ARM.exidx* gnu.linkonce.armexidx.*)
    #endif
    	__exidx_end = .;
    	} GROUP_LINK_IN(ROMABLE_REGION)
    
    	__rodata_region_start = .;
    
    #include <linker/common-rom.ld>
    #include <linker/thread-local-storage.ld>
    
        SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
    	{
    	*(.rodata)
    	*(".rodata.*")
    	*(.gnu.linkonce.r.*)
    
    /* Located in generated directory. This file is populated by the
     * zephyr_linker_sources() Cmake function.
     */
    #include <snippets-rodata.ld>
    
    #include <linker/kobject-rom.ld>
    
    	/*
    	 * For XIP images, in order to avoid the situation when __data_rom_start
    	 * is 32-bit aligned, but the actual data is placed right after rodata
    	 * section, which may not end exactly at 32-bit border, pad rodata
    	 * section, so __data_rom_start points at data and it is 32-bit aligned.
    	 *
    	 * On non-XIP images this may enlarge image size up to 3 bytes. This
    	 * generally is not an issue, since modern ROM and FLASH memory is
    	 * usually 4k aligned.
    	 */
    	. = ALIGN(4);
    	} GROUP_LINK_IN(ROMABLE_REGION)
    
    #include <linker/cplusplus-rom.ld>
    
    	__rodata_region_end = .;
    	MPU_ALIGN(__rodata_region_end -__rom_region_start);
    	__rom_region_end = .;
    
        GROUP_END(ROMABLE_REGION)
    
        /*
         * These are here according to 'arm-zephyr-elf-ld --verbose',
         * before data section.
         */
        /DISCARD/ : {
    	*(.got.plt)
    	*(.igot.plt)
    	*(.got)
    	*(.igot)
    	}
    
        GROUP_START(RAMABLE_REGION)
    
    	. = RAM_ADDR;
    	/* Align the start of image SRAM with the
    	 * minimum granularity required by MPU.
    	 */
    	. = ALIGN(_region_min_align);
    	_image_ram_start = .;
    
    /* Located in generated directory. This file is populated by the
     * zephyr_linker_sources() Cmake function.
     */
    #include <snippets-ram-sections.ld>
    
    #if defined(CONFIG_USERSPACE)
    #define APP_SHARED_ALIGN . = ALIGN(_region_min_align);
    #define SMEM_PARTITION_ALIGN MPU_ALIGN
    
    #include <app_smem.ld>
    
    	_app_smem_size = _app_smem_end - _app_smem_start;
    	_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
    
        SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
    	{
            /*
             * For performance, BSS section is assumed to be 4 byte aligned and
             * a multiple of 4 bytes
             */
            . = ALIGN(4);
    	__bss_start = .;
    	__kernel_ram_start = .;
    
    	*(.bss)
    	*(".bss.*")
    	*(COMMON)
    	*(".kernel_bss.*")
    
    #ifdef CONFIG_CODE_DATA_RELOCATION
    #include <linker_sram_bss_relocate.ld>
    #endif
    
            /*
             * As memory is cleared in words only, it is simpler to ensure the BSS
             * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
    		 */
    	__bss_end = ALIGN(4);
    	} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
    
    #include <linker/common-noinit.ld>
    
    #endif  /* CONFIG_USERSPACE */
    
        GROUP_START(DATA_REGION)
    
        SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
    	{
    	__data_region_start = .;
    	__data_start = .;
    	*(.data)
    	*(".data.*")
    	*(".kernel.*")
    
    /* Located in generated directory. This file is populated by the
     * zephyr_linker_sources() Cmake function.
     */
    #include <snippets-rwdata.ld>
    
    #ifdef CONFIG_CODE_DATA_RELOCATION
    #include <linker_sram_data_relocate.ld>
    #endif
    	__data_end = .;
    
    	} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
        __data_size = __data_end - __data_start;
        __data_load_start = LOADADDR(_DATA_SECTION_NAME);
    
        __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
    
    #include <linker/common-ram.ld>
    #include <linker/kobject-data.ld>
    
    #include <linker/cplusplus-ram.ld>
    
    /* Located in generated directory. This file is populated by the
     * zephyr_linker_sources() Cmake function.
     */
    #include <snippets-data-sections.ld>
    
        __data_region_end = .;
    
    #ifndef CONFIG_USERSPACE
       SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
    	{
            /*
             * For performance, BSS section is assumed to be 4 byte aligned and
             * a multiple of 4 bytes
             */
            . = ALIGN(4);
    	__bss_start = .;
    	__kernel_ram_start = .;
    
    	*(.bss)
    	*(".bss.*")
    	*(COMMON)
    	*(".kernel_bss.*")
    
    #ifdef CONFIG_CODE_DATA_RELOCATION
    #include <linker_sram_bss_relocate.ld>
    #endif
    
            /*
             * As memory is cleared in words only, it is simpler to ensure the BSS
             * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
    		 */
    	__bss_end = ALIGN(4);
    	} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
    
        SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
            {
            /*
             * This section is used for non-initialized objects that
             * will not be cleared during the boot process.
             */
            *(.noinit)
            *(".noinit.*")
    	*(".kernel_noinit.*")
    
    /* Located in generated directory. This file is populated by the
     * zephyr_linker_sources() Cmake function.
     */
    #include <snippets-noinit.ld>
    
            } GROUP_LINK_IN(RAMABLE_REGION)
    #endif /* CONFIG_USERSPACE */
    
        /* Define linker symbols */
    
        _image_ram_end = .;
        _end = .; /* end of image */
    
        __kernel_ram_end = RAM_ADDR + RAM_SIZE;
        __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
    
        GROUP_END(RAMABLE_REGION)
    
    #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
    GROUP_START(ITCM)
    
    	SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))
    	{
    		__itcm_start = .;
    		*(.itcm)
    		*(".itcm.*")
    		__itcm_end = .;
    	} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)
    
    	__itcm_size = __itcm_end - __itcm_start;
    	__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);
    
    GROUP_END(ITCM)
    #endif
    
    #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
    GROUP_START(DTCM)
    
    	SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))
    	{
    		__dtcm_start = .;
    		__dtcm_bss_start = .;
    		*(.dtcm_bss)
    		*(".dtcm_bss.*")
    		__dtcm_bss_end = .;
    	} GROUP_LINK_IN(DTCM)
    
    	SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))
    	{
    		__dtcm_noinit_start = .;
    		*(.dtcm_noinit)
    		*(".dtcm_noinit.*")
    		__dtcm_noinit_end = .;
    	} GROUP_LINK_IN(DTCM)
    
    	SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))
    	{
    		__dtcm_data_start = .;
    		*(.dtcm_data)
    		*(".dtcm_data.*")
    		__dtcm_data_end = .;
    	} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)
    
    	__dtcm_end = .;
    
    	__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);
    
    GROUP_END(DTCM)
    #endif
    
    /* Located in generated directory. This file is populated by the
     * zephyr_linker_sources() Cmake function.
     */
    #include <snippets-sections.ld>
    
    #include <linker/debug-sections.ld>
    
        /DISCARD/ : { *(.note.GNU-stack) }
    
        SECTION_PROLOGUE(.ARM.attributes, 0,)
    	{
    	KEEP(*(.ARM.attributes))
    	KEEP(*(.gnu.attributes))
    	}
    
    /* Must be last in romable region */
    SECTION_PROLOGUE(.last_section,(NOLOAD),)
    {
    } GROUP_LINK_IN(ROMABLE_REGION)
    
    /* To provide the image size as a const expression,
     * calculate this value here. */
    _flash_used = LOADADDR(.last_section) - __rom_region_start;
    
        }
    

    changing the MEMORY section to try to accomodate for my partition:

    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE - 0x2000
    SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
    EXTFLASH (wx) : ORIGIN = 0xfe000, LENGTH = 0x2000

    The hw_settings.c file im trying to test with:
    #include <stdint.h>
    
    const uint32_t var_ext_settings = 666U; 
    
    void function_in_ext_flash(void)
    {
    	printk("Address of %s %p\n", __func__, &function_in_ext_flash);
    	printk("Address of var_ext_sram_data %p (%d)\n", &var_ext_settings, var_ext_settings);
    }
    


    Building it show some memory getting used 
    EXTFLASH:         160 B         8 KB      1.95%

    But currently I'm getting a boot loop with a message:

     Non-secure callable region 0 placed in flash region 3 with size 32.

    Changing the cmakelist file to only EXTFLASH_DATA, doesn't result in this behaviour, but the data is still in the main app memory region and the generated code_relocation.c file has empty functions:
    void data_copy_xip_relocation(void)
    {
    void;
    }
    
    void bss_zeroing_relocation(void)
    {
    return;
    }
    

    And memory region after buillding shows  
    EXTFLASH:          0 GB         8 KB      0.00%

    Any suggestions would be highly appreciated.



  • In last message i said "Changing the cmakelist file to only EXTFLASH_DATA, doesn't result in this behaviour..." It does actually result in the same loop. I must have been flashing something else.

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