nRF9160 - ENABLE Pin functionality, VDD_GPIO power on/power off procedure and timing

[WojciechS]

Hello All,

I have few questions below:

- Does the ENABLE input disconnect the internal power systems completely, or does the circuit remain in some mode and nevertheless draw negligible current?

- Considering the suggestions in Section 11.1 Product Specification V2.1 of the nRF9160, the voltage to the VDD_GPIO pins should be switched on after a certain time, what are these times?

- Should the disconnection of VDD_GPIO occur before the disconnection of VDD?

Thank you.

[Kazi Afroza Sultana]

Hello,

Thanks for your queries. Here are the answers:

1. ''Does the ENABLE input disconnect the internal power systems completely, or does the circuit remain in some mode and nevertheless draw negligible current?''

when enable pin is low it disables nrf9160 and brings it into very low current.

2. ''Considering the suggestions in Section 11.1 Product Specification V2.1 of the nRF9160, the voltage to the VDD_GPIO pins should be switched on after a certain time, what are these times?''

VDD_GPIO can be supplied at the same time as VDD, but not before VDD.

3. Should the disconnection of VDD_GPIO occur before the disconnection of VDD?

yes, VDD_GPIO should be removed before removing VDD (https://infocenter.nordicsemi.com/topic/nwp_037/WP/nwp_037/vdd_gpio.html?cp=2_0_6_2_3_4 )

Thanks.

Best Regards,

Kazi Afroza Sultana