How to select SPI mode for nrf52840

Hi,

I am trying to interface nrf52840 with Arducam mini OV2640 2mp. I am trying to implement SPIM to communicate with the arducam. In the arducam OV2640 datasheet, to enable SPI communication, it is mentioned that "The ArduCAM SPI slave interface is fixed SPI mode 0 with POL = 0 and PHA = 1". In the nRF52840 product specification, different modes are mentioned for configuration as shown in the image below. I am confused which mode of nrf52840  should I select such that it corresponds to Arducam SPI mode POL=0 and PHA=1. 

nrf52840 datasheet

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  • Hi,

    If you want POL=0 and PHA=1, then you should use CPOL=0 and CPHA=1, which is SPI mode 1.

    Typically you can configure the SPI mode used when init the spi driver, something like:

    config_spim.mode = NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.

    If any problems please connect a logic analzer to look at the SPI pins (CLK, MISO and MOSI) along with the chip select pin (CSN).

    Kenneth

  • It is very confusing for me as the clock switches between logic high and logic low in the logic analyser. This is the spi_init function:

    int spi_init(unsigned int pin_cs, unsigned int pin_mosi, unsigned int pin_miso, unsigned int pin_clk)
    {
    	NRF_SPIM3->PSEL.CSN = pin_cs;
    	NRF_SPIM3->PSEL.SCK = pin_clk;
    	NRF_SPIM3->PSEL.MOSI = pin_mosi;
    	NRF_SPIM3->PSEL.MISO = pin_miso;
    
    	/* Change the SPI mode here */
    	NRF_SPIM3->CONFIG = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) |
    			    (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) |
    			    (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos);
    
    	/* Change the frequency here */
    	NRF_SPIM3->FREQUENCY = SPIM_FREQUENCY_FREQUENCY_M4;
    
    	NRF_SPIM3->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
    
    	return 0;
    }

    If I set the CPOL as SPI_CONFIG_CPOL_ActiveLow then I see the clock to be logic high and if I set the CPOL as SPI_CONFIG_CPOL_ActiveHigh then I see teh clock to be logic low in the analyser.

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  • It is very confusing for me as the clock switches between logic high and logic low in the logic analyser. This is the spi_init function:

    int spi_init(unsigned int pin_cs, unsigned int pin_mosi, unsigned int pin_miso, unsigned int pin_clk)
    {
    	NRF_SPIM3->PSEL.CSN = pin_cs;
    	NRF_SPIM3->PSEL.SCK = pin_clk;
    	NRF_SPIM3->PSEL.MOSI = pin_mosi;
    	NRF_SPIM3->PSEL.MISO = pin_miso;
    
    	/* Change the SPI mode here */
    	NRF_SPIM3->CONFIG = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) |
    			    (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) |
    			    (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos);
    
    	/* Change the frequency here */
    	NRF_SPIM3->FREQUENCY = SPIM_FREQUENCY_FREQUENCY_M4;
    
    	NRF_SPIM3->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
    
    	return 0;
    }

    If I set the CPOL as SPI_CONFIG_CPOL_ActiveLow then I see the clock to be logic high and if I set the CPOL as SPI_CONFIG_CPOL_ActiveHigh then I see teh clock to be logic low in the analyser.

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