Configuring internal capacitors for crystal oscillator

[JoakimWSI]

Hello I have some questions regarding configuring nRF5340s crystal resonators internal capacitors.

The configuration is described in the following way:

It is not immediately obvious what is going on here since the configuration contain a lot of variables and magic numbers. The most confusing part to me is the ambiguous naming and description of the variable CAPACITANCE. The first question is:

Should CAPACITANCE contain the desired load capacitance (CL) or the desired external capacitance (C1 and C2) calculated by the equation in figure 22?

Second question:

Are the factory trim XOSC32MTRIM values set by nordic before the chips are delivered or are they part of a calibration procedure that must be done by end customers?

[Sigurd]

Hi,

Should CAPACITANCE contain the desired load capacitance (CL) or the desired external capacitance (C1 and C2) calculated by the equation in figure 22?

It's the C1/C2 value.

Let's say that the load capacitance of the crystal is 8 pF. The load capacitors should be somewhat 2 times the internal capacitance - 4. Which means that the parallel load capacitors should be (2*8pF -4pF)= 12 pF

Then simply set CONFIG_SOC_HFXO_CAP_INT_VALUE_X2 to 24. https://developer.nordicsemi.com/nRF_Connect_SDK/doc/2.1.1/kconfig/index.html#CONFIG_SOC_HFXO_CAP_INT_VALUE_X2

Are the factory trim XOSC32MTRIM values set by nordic before the chips are delivered or are they part of a calibration procedure that must be done by end customers?

They are calibrated and set in production.

BR,

Sigurd

[JoakimWSI]

Datasheet refers that the value should be written to register XOSC32MCAPS, you suggest the config symbol CONFIG_SOC_HFXO_CAP_INT_VALUE_X2, are they equivalent?

Are the Trim values automatically integrated when you use  CONFIG_SOC_HFXO_CAP_INT_VALUE_X2 or should you use the same equation as mentioned in the datasheet?

Whey you say:

"The load capacitors should be somewhat 2 times the internal capacitance - 4. Which means that the parallel load capacitors should be (2*8pF -4pF)= 12 pF"

did you mean:

"The internal capacitors should be somewhat 2 times the load capacitance - 4. Which means that the parallel load capacitors should be (2*8pF -4pF)= 12 pF"

The -4 number you use, is that accounting for the stray capacitance of both the PCB and the input capacitance of the pins or is it only the stray capacitance of the pins?

When you say:

"They are calibrated and set in production."

Do you refer to you production of the chips or our production of PCBs?

BR

Joakim

[Sigurd]

Hi,

JoakimWSI said:

Datasheet refers that the value should be written to register XOSC32MCAPS, you suggest the config symbol CONFIG_SOC_HFXO_CAP_INT_VALUE_X2, are they equivalent?

CONFIG_SOC_HFXO_CAP_INT_VALUE_X2 is CAPACITANCE*2

Capvalue is set for you by the startup code when you set:

CONFIG_SOC_HFXO_CAP_INTERNAL=y

CONFIG_SOC_HFXO_CAP_INT_VALUE_X2= your_CAPACITANCE*2

You can see the code for this here: https://github.com/nrfconnect/sdk-zephyr/blob/v3.1.99-ncs1/soc/arm/nordic_nrf/nrf53/soc.c#L140

The load capacitors(C1/C2) should be somewhat 2 times the load capacitance of the crystal - 4. Which means that the parallel load capacitors should be (2*8pF -4pF)= 12 pF

JoakimWSI said:

The -4 number you use, is that accounting for the stray capacitance of both the PCB and the input capacitance of the pins or is it only the stray capacitance of the pins?

Both(the product specification specifies C_pin to be 2.5 pF, and we can assume that C_pcb are ~1.5 pF).

JoakimWSI said:

Do you refer to you production of the chips or our production of PCBs?

Chips.

BR,

Sigurd