SPI Clock edge too slow

[GLNeedham]

Hi,

We are having some issues communicating with a Winbond W25Q64 flash memory. Using the standard SPI Zephyr drivers an attempt to get the Manufacturer ID returns 0xDC rather than the expected oxEF. By analysing things with both a logic analyser and scope we see that the rise time of the SCL clock signal is around 60ns which is almost twice the allowed time according to the Winbond datasheet.

We also repeated the test on the nRF52832 DK and with the scope on SCL we seem the same problem, removing the scope lead improves things a little so the clock is being affected by the scope capacitance. By setting the nRF52832 SCL GPIO to HIHO the problem is fixed and we see a very rapid rise on the SCL

So, the question is....... is it possible to change the SCL GPIO pin drive characteristics on the nRF9160 within the Zephyr SDK?

Any help gratefully received

Thanks

[Simonr]

Hi Glenn

I think this should be the correct way to sett the drive of GPIOs. As ong as you call the gpio_pin_configure after Zephyr has initialized the drivers/libraries used in your project. To make sure that the GPIO config register (PIN-CNF) is set to high drive you can use a debugger to see the setting of this register. Using the nRF Connect Extension in VS code and the debugger available there should be okay for example.

Best regards,

Simon

[GLNeedham]

Simon,

Thanks for your help. We could not get the gpio_pin_configure() to work in the main code, even after spim initialisation. However, we did change the configuration of the clock pin in the low level SPIM source gpio_pin_configure() function in v2.1.0\modules\hal\nordic\nrfx\drivers\src and that had the desired affect.

With the H1H0 drive set the SPIM works fine.

Thanks again

Glenn

[Simonr]

Glad to hear that Glenn! That should be fine. Let me know if you have any further follow ups.

Best regards,

Simon