[nRF52832] Power-on reset problem?

Question

Dear Support Team, In nRF52832_PS_v1.8.pdf, "18.6.1 Power-on reset" has the following description: 
 A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid supply
range, may result in a system reset 
 Are there any more detailed explanations (such as graph curves) or design suggestions for this description?

Einar Thorsrud · Accepted Answer

Hi Zero, 
 The statement in the product specification is worst case over temperature, voltages, and production variation in silicon. For a typical chip at room temperature it will be in the ~600mV range. We need however to state worst case, since that is what needs to be the design requirement for anyone developing for instance a charge circuit or a system that can switch between battery power and steady power supply. 
 Have in mind that the description is for a step-increase in voltage, this will for instance apply if you change power supply or potentially charge up batteries. It does not affect for instance intermittent voltage transients or ripple in VDD during normal use, this means that ripple due to internal impedance in coin cell or other batteries is not triggering reset. 
 We do not have any graphs that show this (and as mentionned there will be a lot of variations). But there is a figure in the product specification right below the statement in question, which shows the principles of the Power supply supervisor, and this shows the basis for this statement. 
 Br, 
 Einar

[nRF52832] Power-on reset problem?

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