gpio speed problem

[William.wei]

hi support team,

our customer is trying to use gpio to simulate interface for external device communication.

and i tested our 5340dk pin 28 and pin 29, find out that gpio speed is not stable as below:

i have added source code as below:

    #ifdef CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT

    /* For now hardcode to 128MHz */

    nrfx_clock_divider_set(NRF_CLOCK_DOMAIN_HFCLK,

                   NRF_CLOCK_HFCLK_DIV_1);

    #endif

    printk("Starting %s with CPU frequency: %d MHz\n", CONFIG_BOARD, SystemCoreClock/MHZ(1));

and

    unsigned int key = arch_irq_lock();

        NRF_GPIO_Type * reg = NRF_P0;

        reg->OUTSET = ( ((1UL << 28)) );

        reg->OUTSET = (((1UL << 29)));

        pins_state1 = reg->OUT;

        reg->OUTCLR = ( ((1UL << 28)) );

        reg->OUTCLR = (((1UL << 29)));

        pins_state2 = reg->OUT;

        reg->OUTSET = ( ((1UL << 28)) );

        reg->OUTSET = (((1UL << 29)));

        pins_state3 = reg->OUT;

        reg->OUTCLR = ( ((1UL << 28)) );

        reg->OUTCLR = (((1UL << 29)));

        pins_state4 = reg->OUT;

        reg->OUTSET = ( ((1UL << 28)) );

        reg->OUTSET =(((1UL << 29)));

        pins_state5 = reg->OUT;

        reg->OUTCLR = ( ((1UL << 28)) );

        reg->OUTCLR = (((1UL << 29)));

        pins_state6 = reg->OUT;

        reg->OUTSET = ( ((1UL << 28)) );

        reg->OUTSET =(((1UL << 29)));

        pins_state7 = reg->OUT;

        reg->OUTCLR = ( ((1UL << 28)) );

        reg->OUTCLR =(((1UL << 29)));

        pins_state8 = reg->OUT;

   arch_irq_unlock(key);

i don't know why this gpio speed is changing randomly.

Regards,

William.

[hmolesworth]

It is likely that the I/O pin is using the PCLK16M 16MHz clock, so will only transition edges at 62.5nSec intervals. However, I don't see where this is defined in the product spec, or indeed if the PCLK32 or PCLK64 are available for i/o port pin peripheral operation. I/O port pins and PWM may both be limited to 16MHz, whereas TIMER/COUNTER and SPI (for example) can use faster clocks

[William.wei]

hi,

actually the clock is not 16M when i disable cpu at 128M(which means 64M cpu speed), and this gpio speed is as below:

Regards,

William.

[Kazi Afroza Sultana]

Hello William,

I have reproduced the issue and I also have jitter (not stable toggling) for each duty cycle. Since the pins are set with no delay, so we cannot expect stable toggling. To toggle a GPIO without using the CPU, we need to use GPIOTE. CPU and peripheral are on different buses, at different speeds. the peripheral bus is here at 16Mhz, while the CPU is either 128 MHz or 64 MHz.

You need to use either DPPI+TIMER+GPIOTE peripheral or use the PWM peripheral.

You can look at this nrfx sample in zephyr to do that https://github.com/nrfconnect/sdk-zephyr/blob/main/samples/boards/nrf/nrfx/src/main.c . 

In prj.conf file, you need to add this CONFIG_NRFX_TIMER2=y also.

Thanks.

Regards,

Kazi

[hmolesworth]

To clarify for William, the cpu clock is different from the i/o pin peripheral clock. Yes the cpu clock can be 64MHz or 128MHz, but the pin peripheral clock is limited to 16MHz regardless of cpu clock so i/o port pin transitions are limited to a shortest interval of 62.5nSec as I noted earlier. Using the DPPI will not increase the peripheral pin clock above 16MHz and so although it will give better stability and predictability the pin can never transition at other than integer multiples of 62.5nSec intervals. The 16MHz i/o pin peripheral clock is synchronous to the 64MHz or 128MHz cpu clock, and so cannot "slide" to other starting positions for the 62.5nSec tick.