gpio speed problem

[William.wei]

hi support team,

our customer is trying to use gpio to simulate interface for external device communication.

and i tested our 5340dk pin 28 and pin 29, find out that gpio speed is not stable as below:

i have added source code as below:

    #ifdef CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT

    /* For now hardcode to 128MHz */

    nrfx_clock_divider_set(NRF_CLOCK_DOMAIN_HFCLK,

                   NRF_CLOCK_HFCLK_DIV_1);

    #endif

    printk("Starting %s with CPU frequency: %d MHz\n", CONFIG_BOARD, SystemCoreClock/MHZ(1));

and

    unsigned int key = arch_irq_lock();

        NRF_GPIO_Type * reg = NRF_P0;

        reg->OUTSET = ( ((1UL << 28)) );

        reg->OUTSET = (((1UL << 29)));

        pins_state1 = reg->OUT;

        reg->OUTCLR = ( ((1UL << 28)) );

        reg->OUTCLR = (((1UL << 29)));

        pins_state2 = reg->OUT;

        reg->OUTSET = ( ((1UL << 28)) );

        reg->OUTSET = (((1UL << 29)));

        pins_state3 = reg->OUT;

        reg->OUTCLR = ( ((1UL << 28)) );

        reg->OUTCLR = (((1UL << 29)));

        pins_state4 = reg->OUT;

        reg->OUTSET = ( ((1UL << 28)) );

        reg->OUTSET =(((1UL << 29)));

        pins_state5 = reg->OUT;

        reg->OUTCLR = ( ((1UL << 28)) );

        reg->OUTCLR = (((1UL << 29)));

        pins_state6 = reg->OUT;

        reg->OUTSET = ( ((1UL << 28)) );

        reg->OUTSET =(((1UL << 29)));

        pins_state7 = reg->OUT;

        reg->OUTCLR = ( ((1UL << 28)) );

        reg->OUTCLR =(((1UL << 29)));

        pins_state8 = reg->OUT;

   arch_irq_unlock(key);

i don't know why this gpio speed is changing randomly.

Regards,

William.

[hmolesworth]

To clarify for William, the cpu clock is different from the i/o pin peripheral clock. Yes the cpu clock can be 64MHz or 128MHz, but the pin peripheral clock is limited to 16MHz regardless of cpu clock so i/o port pin transitions are limited to a shortest interval of 62.5nSec as I noted earlier. Using the DPPI will not increase the peripheral pin clock above 16MHz and so although it will give better stability and predictability the pin can never transition at other than integer multiples of 62.5nSec intervals. The 16MHz i/o pin peripheral clock is synchronous to the 64MHz or 128MHz cpu clock, and so cannot "slide" to other starting positions for the 62.5nSec tick.