Hi Sir/Madam,
What is the maximum allowed voltage at the below 5pins when nRF5340-QKAA is not powered up?
Thanks.
Regards,
Tze Hao
Hi Sir/Madam,
What is the maximum allowed voltage at the below 5pins when nRF5340-QKAA is not powered up?
Thanks.
Regards,
Tze Hao
Hi,
All pins should be below VDD+03V at all time, so if VDD is 0V, then the maximum voltage is 0.3V on pins.
Kenneth
Hi Kenneth,
Since the maximum voltage is 0.3V at all pins when VDD is 0V,
once the relevant debug pins are connected to the external J-link, the relevant debug pins will be exceeding the maximum voltage, how could we protect those debug pins?
Thanks.
Regards,
Tze Hao
Hi Kenneth,
Since the maximum voltage is 0.3V at all pins when VDD is 0V,
once the relevant debug pins are connected to the external J-link, the relevant debug pins will be exceeding the maximum voltage, how could we protect those debug pins?
Thanks.
Regards,
Tze Hao
Hi,
I do believe some j-link debuggers have level shifters, such that also the target voltage (VTG) is connected to the debugger, in this case the j-link should ensure no voltage is applied on the SWD interface before VDD is applied.
Best regards,
Kenneth