GPIO drive strength breaking change on NCS v2.1 w/ Zephyr 3.1.99

Question

In this commit https://github.com/nrfconnect/sdk-zephyr/commit/d4023b3c1b8c32d978299143125ce5543c9bc6bb and this conflicting commit https://github.com/nrfconnect/sdk-zephyr/commit/2533b13cd21ddc08bec5fd1cc0018ec470eea596 , GPIO_DS_ALT flags were marked deprecated but were actually broken. 
 The legacy GPIO configuration used bits 8, 9, and 10 for debounce, low pos drive, and high pos drive. The new NRF_GPIO_DS_* flags use bits 8 and 9 for low pos drive and high pos drive. 
 Changes to GPIO need to be well documented. The new NRF_GPIO_DS_* flags need to be documented/discoverable without debugging the SDK. The new values don't even match the deprecation message. It looks like the next release will remove the invalid legacy macros, but since v3.1.99-ncs1-1 there are invalid GPIO_DS_ALT or GPIO_DS_DFLT macros. 
 
 ``` 
 * @deprecated Use the GPIO controller/SoC specific `*_GPIO_DS_*` flags instead. 
 ``` 
 
 ``` 
 jwtrueb@dhcp-10-101-37-8 v2.1.2 % rg GPIO_DS zephyr/doc/releases/release-notes-3.1.rst 123: * Deprecated the ``GPIO_INT_DEBOUNCE`` flag and the ``GPIO_DS_*`` and 
 zephyr/include/zephyr/drivers/gpio.h 43: * @deprecated Use the GPIO controller/SoC specific `*_GPIO_DS_*` flags instead. 47:#define GPIO_DS_LOW_POS 9 __DEPRECATED_MACRO 48:#define GPIO_DS_LOW_MASK (0x1U << GPIO_DS_LOW_POS) __DEPRECATED_MACRO 49:#define GPIO_DS_HIGH_POS 10 __DEPRECATED_MACRO 50:#define GPIO_DS_HIGH_MASK (0x1U << GPIO_DS_HIGH_POS) __DEPRECATED_MACRO 51:#define GPIO_DS_MASK (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK) __DEPRECATED_MACRO 53:#define GPIO_DS_DFLT_LOW (0x0U << GPIO_DS_LOW_POS) __DEPRECATED_MACRO 54:#define GPIO_DS_ALT_LOW (0x1U << GPIO_DS_LOW_POS) __DEPRECATED_MACRO 55:#define GPIO_DS_DFLT_HIGH (0x0U << GPIO_DS_HIGH_POS) __DEPRECATED_MACRO 56:#define GPIO_DS_ALT_HIGH (0x1U << GPIO_DS_HIGH_POS) __DEPRECATED_MACRO 57:#define GPIO_DS_DFLT (GPIO_DS_DFLT_LOW | GPIO_DS_DFLT_HIGH) __DEPRECATED_MACRO 58:#define GPIO_DS_ALT (GPIO_DS_ALT_LOW | GPIO_DS_ALT_HIGH) __DEPRECATED_MACRO 
 zephyr/include/zephyr/dt-bindings/gpio/espressif-esp32-gpio.h 23:#define ESP32_GPIO_DS_POS 9 24:#define ESP32_GPIO_DS_MASK (0x3U << ESP32_GPIO_DS_POS) 28:#define ESP32_GPIO_DS_DFLT (0x0U << ESP32_GPIO_DS_POS) 31:#define ESP32_GPIO_DS_ALT (0x3U << ESP32_GPIO_DS_POS) 
 zephyr/include/zephyr/dt-bindings/gpio/nxp-kinetis-gpio.h 23:#define KINETIS_GPIO_DS_POS 9 24:#define KINETIS_GPIO_DS_MASK (0x3U << KINETIS_GPIO_DS_POS) 28:#define KINETIS_GPIO_DS_DFLT (0x0U << KINETIS_GPIO_DS_POS) 31:#define KINETIS_GPIO_DS_ALT (0x3U << KINETIS_GPIO_DS_POS) 
 zephyr/include/zephyr/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h 32:#define CC13XX_CC26XX_GPIO_DS_POS 9 33:#define CC13XX_CC26XX_GPIO_DS_MASK (0x3U << CC13XX_CC26XX_GPIO_DS_POS) 37:#define CC13XX_CC26XX_GPIO_DS_DFLT (0x0U << CC13XX_CC26XX_GPIO_DS_POS) 40:#define CC13XX_CC26XX_GPIO_DS_ALT (0x3U << CC13XX_CC26XX_GPIO_DS_POS) 
 zephyr/drivers/ieee802154/ieee802154_mcr20a_regs.h 281:#define MCR20A_GPIO_DS (0x2e) 495:#define MCR20A_GPIO_DS8 BIT(7) 496:#define MCR20A_GPIO_DS7 BIT(6) 497:#define MCR20A_GPIO_DS6 BIT(5) 498:#define MCR20A_GPIO_DS5 BIT(4) 499:#define MCR20A_GPIO_DS4 BIT(3) 500:#define MCR20A_GPIO_DS3 BIT(2) 501:#define MCR20A_GPIO_DS2 BIT(1) 502:#define MCR20A_GPIO_DS1 BIT(0) 515:#define MCR20A_MISC_PAD_CTRL_NON_GPIO_DS BIT(1) 
 zephyr/drivers/gpio/gpio_andes_atcgpio100.c 63:#define GPIO_DSET(dev) (GPIO_BASE(dev) + REG_DSET) 122: OUTWORD(GPIO_DSET(port), pin_mask); 193: OUTWORD(GPIO_DSET(port), pins); 
 zephyr/drivers/gpio/gpio_cc13xx_cc26xx.c 79: switch (flags & CC13XX_CC26XX_GPIO_DS_MASK) { 80: case CC13XX_CC26XX_GPIO_DS_DFLT: 83: case CC13XX_CC26XX_GPIO_DS_ALT: 
 zephyr/drivers/gpio/gpio_mcux.c 102: switch (flags & KINETIS_GPIO_DS_MASK) { 103: case KINETIS_GPIO_DS_DFLT: 107: case KINETIS_GPIO_DS_ALT: 
 zephyr/drivers/gpio/gpio_esp32.c 182: switch (flags & ESP32_GPIO_DS_MASK) { 183: case ESP32_GPIO_DS_DFLT: 195: case ESP32_GPIO_DS_ALT: 
 modules/tee/tf-m/trusted-firmware-m/platform/ext/target/cypress/psoc64/Device/Include/gpio_psoc6_02_124_bga.h 573: HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 
 ```