NRF51822 - Programming flash via SWD

[Fontanelli]

In the NRF51822 reference manual, the debug interface mode initiation routine is described as follow:

150 clock cycles with SWDIO=1.

I have already verified that a standard Cortex M0 debug interface initialization (with the JTAG to SWD switching routine) is also working.

Can be considered the standard Cortex M0 debug interface initialization according to the flash programming specification?

[RK]

Not quite. The standard ARM SWD debug port reset sequence is at least 50 clock cycles with SWDIO=1. As you correctly state, the NRF51 specifies 150 cycles which allows the debug port enough time to power up and capture the ARM-required 50.

In practice debuggers usually reset the device once, then try sending the debug port a command and if it doesn't reply, reset it again. The JTAG->SWD sequence you mention also starts with a 50 cycle reset, then the switching bit sequence, then another reset, and that entire sequence can be repeated if the DAP doesn't respond. Most of them also clock more than the required 50 cycles.

Given that the debug interface is powered up on the first clock with SWDIO=1 and 150 clocks is the max required at 125kHz for it to be guaranteed to detect the 50-clock reset sequence, in practice the nrf51 is awake in time to capture one of the reset sequences, even if not the first one.

To follow the spec exactly you should clock 150 of them, my empirical experience is that the debug interface wakes up very quickly and the second ARM 50 clock reset sequence gets detected.