Dear all,
I have written some code that controls the SPIS and allows it to transfer data as if it were a master. I am generating the SPIS clock from one timer, and I am looping back a pin to control the CSN line for the SPIS. The CSN is controlled by a high priority interrupt source, and my SPIS interrupt is a low priority interrupt. In the high priority interrupt source I am deasserting the CSN line, grabbing the read data and putting it in a FIFO and then reasserting the CSN pin. I know in this interrupt that all the data will be transferred.
In doing this I do not get an SPIS interrupt being generated. I do see it if the CSN pin is not toggled quite so fast n other sections of my code. I do get repeating transfers of data using this method.
Is this a known issue? I was expecting the END interrupt to be latching, not dependent on whether a new transaction had been started. Similarly, I am releasing the semaphore in this high level interrupt too.
Interested in your response,
Peter